Datasheet

PIC18F97J60 FAMILY
DS39762F-page 430  2011 Microchip Technology Inc.
FIGURE 28-1: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED
(ENVREG TIED TO V
DD)
FIGURE 28-2: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED
(ENVREG TIED TO V
SS)
Frequency
Voltage (VDD)
(1)
4.0V
2.0V
41.6667 MHz
3.5V
3.0V
2.5V
3.6V
PIC18F6XJ6X/8XJ6X/9XJ6X
2.7V
0
Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset
before V
DD reaches a level at which full-speed operation is not possible.
Frequency
Voltage (VDDCORE)
(1)
3.00V
2.00V
41.6667 MHz
2.75V
2.50V
2.25V
2.7V
4 MHz
2.35V
Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
V
DDCOREVDD3.6V.
For frequencies between 4 MHz and 41.6667 MHz, F
MAX = (107.619 MHz/V) * (VDDCORE – 2V) + 4 MHz.
PIC18F6XJ6X/8XJ6X/9XJ6X