Datasheet

PIC18F97J60 FAMILY
DS39762F-page 42 2011 Microchip Technology Inc.
NC 9 No connect.
VSS 15, 36, 40,
60, 65, 85
P Ground reference for logic and I/O pins.
V
DD 17, 37, 59,
62, 86
P Positive supply for peripheral digital logic and I/O pins.
AV
SS 31 P Ground reference for analog modules.
AV
DD 30 P Positive supply for analog modules.
ENVREG 29 I ST Enable for on-chip voltage regulator.
V
DDCORE/VCAP
VDDCORE
VCAP
16
P
P
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
V
SSPLL 82 P Ground reference for Ethernet PHY PLL.
VDDPLL 81 P Positive 3.3V supply for Ethernet PHY PLL.
V
SSTX 79 P Ground reference for Ethernet PHY transmit subsystem.
VDDTX 76 P Positive 3.3V supply for Ethernet PHY transmit subsystem.
V
SSRX 72 P Ground reference for Ethernet PHY receive subsystem.
VDDRX 75 P Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS 80 I Analog Bias current for Ethernet PHY. Must be tied to V
SS via a resistor;
see Section 19.0 “Ethernet Module” for specification.
TPOUT+ 78 O Ethernet differential signal output.
TPOUT- 77 O Ethernet differential signal output.
TPIN+ 74 I Analog Ethernet differential signal input.
TPIN- 73 I Analog Ethernet differential signal input.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).