Datasheet

 2011 Microchip Technology Inc. DS39762F-page 41
PIC18F97J60 FAMILY
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
49
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
RJ1/OE
RJ1
OE
50
I/O
O
ST
—
Digital I/O.
External memory output enable.
RJ2/WRL
RJ2
WRL
66
I/O
O
ST
—
Digital I/O.
External memory write low control.
RJ3/WRH
RJ3
WRH
61
I/O
O
ST
—
Digital I/O.
External memory write high control.
RJ4/BA0
RJ4
BA0
47
I/O
O
ST
—
Digital I/O.
External Memory Byte Address 0 control.
RJ5/CE
RJ5
CE
48
I/O
O
ST
—
Digital I/O
External memory chip enable control.
RJ6/LB
RJ6
LB
58
I/O
O
ST
—
Digital I/O.
External memory low byte control.
RJ7/UB
RJ7
UB
39
I/O
O
ST
—
Digital I/O.
External memory high byte control.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).