Datasheet

PIC18F97J60 FAMILY
DS39762F-page 370  2011 Microchip Technology Inc.
25.4 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an Oscillator Start-up Timer
delay, Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
25.4.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 4.1.4 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS<1:0> bit settings, or issue SLEEP instructions,
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 25-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1
Q3 Q4
OSC1
Peripheral
Program
PC PC + 2
INTRC
PLL Clock
Q1
PC + 6
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 4
Clock
Counter
Q2
Q2
Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TPLL
(1)
12 n-1n
Clock
OSTS bit Set
Transition
TOST
(1)