Datasheet

 2011 Microchip Technology Inc. DS39762F-page 37
PIC18F97J60 FAMILY
PORTE is a bidirectional I/O port.
RE0/AD8/RD/P2D
RE0
AD8
RD
P2D
4
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 8.
Read control for Parallel Slave Port.
ECCP2 PWM Output D.
RE1/AD9/WR
/P2C
RE1
AD9
WR
P2C
3
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 9.
Write control for Parallel Slave Port.
ECCP2 PWM Output C.
RE2/AD10/CS
/P2B
RE2
AD10
CS
P2B
98
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 10.
Chip select control for Parallel Slave Port.
ECCP2 PWM Output B.
RE3/AD11/P3C
RE3
AD11
P3C
(3)
97
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 11.
ECCP3 PWM Output C.
RE4/AD12/P3B
RE4
AD12
P3B
(3)
96
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 12.
ECCP3 PWM Output B.
RE5/AD13/P1C
RE5
AD13
P1C
(3)
95
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 13.
ECCP1 PWM Output C.
RE6/AD14/P1B
RE6
AD14
P1B
(3)
94
I/O
I/O
O
ST
TTL
—
Digital I/O.
External Memory Address/Data 14.
ECCP1 PWM Output B.
RE7/AD15/ECCP2/P2A
RE7
AD15
ECCP2
(4)
P2A
(4)
93
I/O
I/O
I/O
O
ST
TTL
ST
—
Digital I/O.
External Memory Address/Data 15.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM Output A.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).