Datasheet

 2011 Microchip Technology Inc. DS39762F-page 369
PIC18F97J60 FAMILY
25.3 On-Chip Voltage Regulator
All of the PIC18F97J60 family devices power their core
digital logic at a nominal 2.5V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC18F97J60 family incor-
porate an on-chip regulator that allows the device to
run its core logic from V
DD.
The regulator is controlled by the ENVREG pin. Tying
V
DD to the pin enables the regulator, which in turn,
provides power to the core from the other V
DD pins.
When the regulator is enabled, a low-ESR filter capacitor
must be connected to the VDDCORE/VCAP pin
(Figure 25-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor
is provided in Section 28.3 “DC Characteristics:
PIC18F97J60 Family (Industrial)”.
If ENVREG is tied to V
SS, the regulator is disabled. In
this case, separate power for the core logic, at a nomi-
nal 2.5V, must be supplied to the device on the
V
DDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the V
DDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 25-2 for possible
configurations.
25.3.1 ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F97J60
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a regulated level, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR
flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 5.4 “Brown-out Reset (BOR)” and
Section 5.4.1 “Detecting BOR”. The Brown-out
Reset voltage levels are specific in Section 28.1 “DC
Characteristics: Supply Voltage, PIC18F97J60
Family (Industrial)”
25.3.2 POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
DDCORE must
never exceed V
DD by 0.3 volts.
FIGURE 25-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC18FXXJ6X
3.3V
(1)
2.5V
(1)
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC18FXXJ6X
CF
3.3V
Regulator Enabled (ENVREG tied to VDD):
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC18FXXJ6X
2.5V
(1)
(VDD > VDDCORE)
Note 1: These are typical operating voltages. Refer
to Section 28.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of V
DD and VDDCORE.
(V
DD = VDDCORE)