Datasheet

PIC18F97J60 FAMILY
DS39762F-page 36  2011 Microchip Technology Inc.
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
AD0
PSP0
92
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 0.
Parallel Slave Port data.
RD1/AD1/PSP1
RD1
AD1
PSP1
91
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 1.
Parallel Slave Port data.
RD2/AD2/PSP2
RD2
AD2
PSP2
90
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 2.
Parallel Slave Port data.
RD3/AD3/PSP3
RD3
AD3
PSP3
89
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External Memory Address/Data 3.
Parallel Slave Port data.
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
88
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External Memory Address/Data 4.
Parallel Slave Port data.
SPI data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
AD5
PSP5
SDI2
SDA2
87
I/O
I/O
I/O
I
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External Memory Address/Data 5.
Parallel Slave Port data.
SPI data in.
I
2
C™ data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
AD6
PSP6
SCK2
SCL2
84
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External Memory Address/Data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C™ mode.
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
83
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External Memory Address/Data 7.
Parallel Slave Port data.
SPI slave select input.
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).