Datasheet

PIC18F97J60 FAMILY
DS39762F-page 346  2011 Microchip Technology Inc.
22.5 A/D Conversions
Figure 22-3 shows the operation of the A/D Converter
after the GO/DONE
bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 22-4 shows the operation of the A/D Converter
after the GO/DONE
bit has been set, the ACQT<2:0> bits
are set to ‘010’ and a 4 T
AD acquisition time has been
selected before the conversion starts.
Clearing the GO/DONE
bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
22.6 Use of the ECCP2 Trigger
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE
bit
will be set, starting the A/D acquisition and conversion
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
ACQ time is selected before
the Special Event Trigger sets the GO/DONE
bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
FIGURE 22-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 22-4: A/D CONVERSION T
AD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1
TAD2
TAD3
TAD4 TAD5
TAD6 TAD7
TAD8 TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY – TAD
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
1
2
3 4
5
6 7
8 11
Set GO/DONE bit
(Holding capacitor is disconnected)
9 10
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
T
ACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b0b9
b6
b5 b4
b3
b2
b1
b8
b7