Datasheet

 2011 Microchip Technology Inc. DS39762F-page 329
PIC18F97J60 FAMILY
FIGURE 21-6: EUSARTx RECEIVE BLOCK DIAGRAM
FIGURE 21-7: ASYNCHRONOUS RECEPTION, RXDTP = 0 (RXx NOT INVERTED)
TABLE 21-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTIO
N
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71
IPR1
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71
PIR3
SSP2IF BCL2IF RC2IF
(1)
TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71
PIE3
SSP2IE BCL2IE RC2IE
(1)
TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71
IPR3
SSP2IP BCL2IP RC2IP
(1)
TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71
RCREGx EUSARTx Receive Register 71
TXSTAx
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71
BAUDCONx ABDOVF RCIDL RXDTP
TXCKP BRG16 — WUE ABDEN 72
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
x64 Baud Rate CLK
Baud Rate Generator
RXx
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D RCREGx Register
FIFO
Interrupt
RCxIF
RCxIE
Data Bus
8
 64
 16
or
Stop Start(8) 7 1 0
RX9

SPBRGxSPBRGHx
BRG16
or
 4
RXDTP
Start
bit bit 7/8bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit
Start
bitbit 7/8 Stop
bit
RXx (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREGx
Word 2
RCREGx
Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.