Datasheet

PIC18F97J60 FAMILY
DS39762F-page 326  2011 Microchip Technology Inc.
FIGURE 21-3: EUSARTx TRANSMIT BLOCK DIAGRAM
FIGURE 21-4: ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TXx NOT INVERTED)
FIGURE 21-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK), TXCKP = 0
(TXx NOT INVERTED)
TXxIF
TXxIE
Interrupt
TXEN
Baud Rate CLK
SPBRGx
Baud Rate Generator
TX9D
MSb
LSb
Data Bus
TXREGx Register
TSR Register
(8)
0
TX9
TRMT SPEN
TXx pin
Pin Buffer
and Control
8

SPBRGHx
BRG16
TXCKP
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Stop bit
Word 1
Transmit Shift Reg.
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Stop bit Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit