Datasheet

 2011 Microchip Technology Inc. DS39762F-page 313
PIC18F97J60 FAMILY
TABLE 20-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71
IPR1
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71
PIR2 OSCFIF CMIF ETHIF rBCL1IF— TMR3IF CCP2IF 71
PIE2
OSCFIE CMIE ETHIE rBCL1IE— TMR3IE CCP2IE 71
IPR2 OSCFIP CMIP ETHIP rBCL1IP— TMR3IP CCP2IP 71
PIR3 SSP2IF
(1)
BCL2IF
(1)
RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71
PIE3 SSP2IE
(1)
BCL2IE
(1)
RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71
IPR3 SSP2IP
(1)
BCL2IP
(1)
RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71
TRISD
TRISD7 TRISD6
(1)
TRISD5
(1)
TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71
SSP1BUF MSSP1 Receive Buffer/Transmit Register 70
SSP1ADD MSSP1 Address Register (I
2
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
2
C Master mode) 73
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 70
GCEN
ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN 70
SSP1STAT SMP CKE D/A
PSR/WUA BF 70
SSP2BUF MSSP2 Receive Buffer/Transmit Register 70
SSP2ADD MSSP2 Address Register (I
2
C Slave mode), MSSP2 Baud Rate Reload Register (I
2
C Master mode) 73
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 73
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 73
GCEN
ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN 73
SSP2STAT SMP CKE D/A
PSR/WUA BF 73
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by the MSSP module in I
2
C™ mode.
Note 1: These bits are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
2: Alternate bit definitions in I
2
C™ Slave mode.