Datasheet

PIC18F97J60 FAMILY
DS39762F-page 300  2011 Microchip Technology Inc.
20.4.7 BAUD RATE
In I
2
C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 20-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
CY) on the Q2 and Q4 clocks. In I
2
C Master mode, the
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK
), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 20-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
20.4.7.1 Baud Rate and Module
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
2
C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
FIGURE 20-19: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 20-3: I
2
C™ CLOCK RATE w/BRG
FOSC BRG Value
F
SCL
(2 Rollovers of BRG)
41.667 MHz 19h 400 kHz
(1)
41.667 MHz 67h 100 kHz
31.25 MHz 13h 400 kHz
(1)
31.25 MHz 4Dh 100 kHz
20.833 MHz 09h 400 kHz
(1)
20.833 MHz 33h 100 kHz
Note 1: The I
2
C™ interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
SSPM<3:0>
BRG Down Counter
CLKO
F
OSC/4
SSPxADD<6:0>
SSPM<3:0>
SCLx
Reload
Control
Reload