Datasheet

PIC18F97J60 FAMILY
DS39762F-page 258  2011 Microchip Technology Inc.
To enable flow control in Full-Duplex mode, set the
TXPAUS and RXPAUS bits in the MACON1 register.
Then, at any time that the receiver buffer is running out
of space, set the Flow Control Enable bits, FCEN<1:0>
(EFLOCON<1:0>). The module will automatically finish
transmitting anything that was in progress and then
send a valid pause frame, loaded with the selected
pause timer value. Depending on the mode selected,
the application may need to eventually clear Flow
Control mode by again writing to the FCEN bits.
When the RXPAUS bit is set and a valid pause frame
arrives with a non-zero pause timer value, the module
will automatically inhibit transmissions. If the TXRTS bit
becomes set to send a packet, the hardware will simply
wait until the pause timer expires before attempting to
send the packet and subsequently, clearing the TXRTS
bit. Normally, this is transparent to the microcontroller,
and it will never know that a pause frame had been
received. Should it be desirable to know when the MAC
is paused or not, the user should set the PASSALL bit
(MACON1<1>), then manually interpret the pause
control frames which may arrive.
TABLE 19-8: SUMMARY OF REGISTERS USED WITH FLOW CONTROL
REGISTER 19-19: EFLOCON: ETHERNET FLOW CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 R-0 R/W-0 R/W-0
— — — — — r FCEN1 FCEN0
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 Reserved: Do not use
bit 1-0 FCEN<1:0>: Flow Control Enable bits
When FULDPX (MACON3<0>) =
1:
11 = Send one pause frame with a ‘0’ timer value and then turn flow control off
10 = Send pause frames periodically
01 = Send one pause frame then turn flow control off
00 = Flow control off
When FULDPX (MACON3<0>) =
0:
x1 = Flow control on
x0 = Flow control off
Register
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page:
ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 70
MACON1
— — — r TXPAUS RXPAUS PASSALL MARXEN 75
MABBIPG
— BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 75
EFLOCON
— — — — — r FCEN1 FCEN0 75
EPAUSL Pause Timer Value Register Low Byte (EPAUS<7:0>) 75
EPAUSH Pause Timer Value Register High Byte (EPAUS<15:8>) 75
Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.