Datasheet

PIC18F97J60 FAMILY
DS39762F-page 252  2011 Microchip Technology Inc.
19.5.3 RECEIVING PACKETS
Assuming that the receive buffer has been initialized,
the MAC has been properly configured and the receive
filters have been configured, the application should
perform these steps to receive Ethernet packets:
1. Set the PKTIE and ETHIE bits to generate an
Ethernet interrupt whenever a packet is received
(if desired).
2. Clear the RXERIF flag and set both RXERIE
and ETHIE to generate an interrupt whenever a
packet is dropped, due to insufficient buffer
space or memory access bandwidth (if desired).
3. Enable reception by setting the RXEN bit
(ECON1<2>).
After setting RXEN, the Duplex mode and the Receive
Buffer Start and End Pointers should not be modified.
Additionally, to prevent unexpected packets from arriv-
ing, it is recommended that RXEN be cleared before
altering the receive filter configuration (ERXFCON) and
MAC address.
After reception is enabled, packets which are not
filtered out will be written into the circular receive buffer.
Any packet which does not meet the necessary filter
criteria will be discarded and the application will not
have any means of identifying that a packet was thrown
away. When a packet is accepted and completely
written into the buffer:
• The EPKTCNT register is incremented
• The PKTIF bit is set
• An interrupt is generated (if enabled)
• The Hardware Write Pointers, ERXWRPT, are
automatically advanced
19.5.3.1 Receive Packet Layout
Figure 19-11 shows the layout of a received packet.
The packets are preceded by a 6-byte header which
contains a Next Packet Pointer in addition to a receive
status vector which contains receive statistics,
including the packet’s size. The receive status vectors
are shown in Tab le 19-5.
If the last byte in the packet ends on an odd value
address, the hardware will automatically add a padding
byte when advancing the Hardware Write Pointer. As
such, all packets will start on an even boundary.
FIGURE 19-11: SAMPLE RECEIVE PACKET LAYOUT
Low Byte
High Byte
rsv[7:0]
rsv[15:8]
data[m-3]
data[m-2]
data[m-1]
data[m]
Address Memory Description
1020h
1021h
1022h
1023h
105Ah
105Bh
105Ch
1059h
10h
5Eh
Next Packet Pointer
Packet Data: Destination Address,
Receive Status Vector
crc[31:24]
crc[23:16]
crc[15:8]
crc[7:0]
105Eh
Start of the Next Packet
rsv[23:16]
rsv[30:24]
1024h
1025h
data[1]
1026h
data[2]
1027h
status[7:0]
status[15:8]
status[23:16]
status[31:24]
105Dh
Byte Skipped to Ensure
Even Buffer Address
101Fh
End of the Previous PacketPacket N – 1
Source Address, Type/Length, Data,
Padding, CRC
Packet N
Packet N + 1