Datasheet

PIC18F97J60 FAMILY
DS39762F-page 242  2011 Microchip Technology Inc.
REGISTER 19-16: PHIE: PHY INTERRUPT ENABLE REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
r r r r r r r r
bit 15 bit 8
R-0 R-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0
r r rPLNKIEr rPGEIEr
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Reserved: Write as ‘0’, ignore on read
bit 5 Reserved: Maintain as ‘0’
bit 4 PLNKIE: PHY Link Change Interrupt Enable bit
1 = PHY link change interrupt is enabled
0 = PHY link change interrupt is disabled
bit 3-2 Reserved: Write as ‘0’, ignore on read
bit 1 PGEIE: PHY Global Interrupt Enable bit
1 = PHY interrupts are enabled
0 = PHY interrupts are disabled
bit 0 Reserved: Maintain as ‘0’
REGISTER 19-17: PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER
R-x R-x R-x R-x R-x R-x R-x R-x
r r r r r r r r
bit 15 bit 8
R-x R-x R-0 R/SC-0 R-0 R/SC-0 R-x R-0
r r rPLNKIFrPGIFr r
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit SC = Self-Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Reserved: Ignore on read
bit 5 Reserved: Read as ‘0’
bit 4 PLNKIF: PHY Link Change Interrupt Flag bit
1 = PHY link status has changed since PHIR was last read; resets to ‘0’ when read
0 = PHY link status has not changed since PHIR was last read
bit 3 Reserved: Read as ‘0’
bit 2 PGIF: PHY Global Interrupt Flag bit
1 = One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read
0 = No PHY interrupts have occurred
bit 1 Reserved: Ignore on read
bit 0 Reserved: Read as ‘0’