Datasheet

PIC18F97J60 FAMILY
DS39762F-page 24  2011 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG4/CCP5/P1D
RG4
CCP5
P1D
8
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM Output D.
V
SS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
V
DD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.
AV
DD 19 P — Positive supply for analog modules.
ENVREG 18 I ST Enable for on-chip voltage regulator.
V
DDCORE/VCAP
VDDCORE
VCAP
10
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
V
SSPLL 55 P — Ground reference for Ethernet PHY PLL.
VDDPLL 54 P — Positive 3.3V supply for Ethernet PHY PLL.
V
SSTX 52 P — Ground reference for Ethernet PHY transmit subsystem.
VDDTX 49 P — Positive 3.3V supply for Ethernet PHY transmit subsystem.
V
SSRX 45 P — Ground reference for Ethernet PHY receive subsystem.
VDDRX 48 P — Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS 53 I Analog Bias current for Ethernet PHY. Must be tied to V
SS via a resistor;
see Section 19.0 “Ethernet Module” for specification.
TPOUT+ 51 O — Ethernet differential signal output.
TPOUT- 50 O — Ethernet differential signal output.
TPIN+ 47 I Analog Ethernet differential signal input.
TPIN- 46 I Analog Ethernet differential signal input.
TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)