Datasheet

 2011 Microchip Technology Inc. DS39762F-page 239
PIC18F97J60 FAMILY
19.3 Ethernet Interrupts
The Ethernet module can generate multiple interrupt
conditions. To accommodate all of these sources, the
module has its own interrupt logic structure, similar to
that of the microcontroller. Separate sets of registers
are used to enable and flag different interrupt
conditions.
The EIE register contains the individual interrupt
enable bits for each source, while the EIR register con-
tains the corresponding interrupt flag bits. When an
interrupt occurs, the interrupt flag is set. If the interrupt
is enabled in the EIE register, and the corresponding
ETHIE Global Interrupt Enable bit is set, the micro-
controller’s master Ethernet Interrupt Flag (ETHIF) is
set, as appropriate (see Figure 19-7).
19.3.1 CONTROL INTERRUPT (ETHIE)
The four registers associated with the control interrupts
are shown in Register 19-14 through Register 19-17.
FIGURE 19-7: ETHERNET MODULE INTERRUPT LOGIC
Note: Except for the LINKIF interrupt flag,
interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the associ-
ated global enable bit. User software
should ensure the appropriate interrupt
flag bits are clear prior to enabling an
interrupt. This feature allows for software
polling.
PKTIF
PKTIE
DMAIF
DMAIE
LINKIE
TXIF
TXIE
Set ETHIF
ETHIE
TXERIF
TXERIE
RXERIF
RXERIE
LINKIF
PGIF
PGEIE
PLNKIF
PLNKIE