Datasheet

PIC18F97J60 FAMILY
DS39762F-page 236  2011 Microchip Technology Inc.
REGISTER 19-11: PHCON2: PHY CONTROL REGISTER 2
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— FRCLNK r r r r r HDLDIS
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
r r r RXAPDIS r r r r
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 FRCLNK: PHY Force Linkup bit
1 = Force linkup even when no link partner is detected (transmission is always allowed)
0 = Normal operation (PHY blocks transmission attempts unless a link partner is attached)
bit 13-9 Reserved: Write as ‘0’
bit 8 HDLDIS: PHY Half-Duplex Loopback Disable bit
1 = Normal PHY operation
0 = Reserved
bit 7-5 Reserved: Write as ‘0’
bit 4 RXAPDIS: RX+/RX- Operating mode bit
1 = Normal operation
0 = Reserved
bit 3-0 Reserved: Write as ‘0’
Note: Improper Ethernet operation may result if HDLDIS or RXAPDIS is cleared, which is the Reset default.
Always initialize these bits set before using the Ethernet module.