Datasheet

 2011 Microchip Technology Inc. DS39762F-page 235
PIC18F97J60 FAMILY
REGISTER 19-9: PHCON1: PHY CONTROL REGISTER 1
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0
r r — — r r — PDPXMD
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
r — — — — — — —
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Reserved: Write as ‘0’
bit 13-12 Unimplemented: Read as ‘0’
bit 11-10 Reserved: Write as ‘0’
bit 9 Unimplemented: Read as ‘0’
bit 8 PDPXMD: PHY Duplex Mode bit
1 = PHY operates in Full-Duplex mode; application must also set FULDPX (MACON3<0>)
0 = PHY operates in Half-Duplex mode, application must also clear FULDP
bit 7 Reserved: Maintain as ‘0’
bit 6-0 Unimplemented: Read as ‘0’
REGISTER 19-10: PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1
U-0 U-0 U-0 R-1 R-1 U-0 U-0 U-0
— — — r r — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/LL-0 R/LH-0 U-0
— — — — —LLSTAT r —
bit 7 bit 0
Legend: ‘1’ = Bit is set r = Reserved bit
R = Read-only bit ‘0’ = Bit is cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR R/L = Read-Only Latch bit LL = Latches Low bit LH = Latches High bit
bit 15-13 Unimplemented: Read as ‘0’
bit 12-11 Reserved: Read as ‘1’
bit 10-3 Unimplemented: Read as ‘0’
bit 2 LLSTAT: PHY Latching Link Status bit
1 = Link is up and has been up continously since PHSTAT1 was last read
0 = Link is down or was down for a period since PHSTAT1 was last read
bit 1 Reserved: Ignore on read
bit 0 Unimplemented: Read as ‘0’