Datasheet

PIC18F97J60 FAMILY
DS39762F-page 230  2011 Microchip Technology Inc.
REGISTER 19-5: MACON3: MAC CONTROL REGISTER 3
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 PADCFG<2:0>: Automatic Pad and CRC Configuration bits
111 = All short frames are zero-padded to 64 bytes and a valid CRC will then be appended
110 = No automatic padding of short frames
101 = MAC automatically detects VLAN protocol frames which have a 8100h type field and auto-
matically pad to 64 bytes. If the frame is not a VLAN frame, it is padded to 60 bytes. After padding,
a valid CRC is appended.
100 = No automatic padding of short frames
011 = All short frames are zero-padded to 64 bytes and a valid CRC is appended
010 = No automatic padding of short frames
001 = All short frames are zero-padded to 60 bytes and a valid CRC is appended
000 = No automatic padding of short frames
bit 4 TXCRCEN: Transmit CRC Enable bit
1 = MAC appends a valid CRC to all frames transmitted, regardless of the PADCFG<2:0> bits.
TXCRCEN must be set if the PADCFG bits specify that a valid CRC is appended.
0 = MAC does not append a CRC. The last 4 bytes are checked and if it is an invalid CRC, it is
reported in the transmit status vector.
bit 3 PHDREN: Proprietary Header Enable bit
1 = Frames presented to the MAC contain a 4-byte proprietary header which is not used when
calculating the CRC
0 = No proprietary header is present; the CRC covers all data (normal operation)
bit 2 HFRMEN: Huge Frame Enable bit
1 = Jumbo frames and frames of any illegal size are allowed to be transmitted and received
0 = Frames bigger than MAMXFL are truncated when transmitted or received
bit 1 FRMLNEN: Frame Length Checking Enable bit
1 = The type/length field of transmitted and received frames is checked. If it represents a length, the
frame size is compared and mismatches are reported in the transmit/receive status vector.
0 = Frame lengths are not compared with the type/length field
bit 0 FULDPX: MAC Full-Duplex Enable bit
1 = MAC operates in Full-Duplex mode; application must also set PDPXMD (PHCON1<8>)
0 = MAC operates in Half-Duplex mode; application must also clear PDPXMD