Datasheet

PIC18F97J60 FAMILY
DS39762F-page 228  2011 Microchip Technology Inc.
REGISTER 19-2: ECON2: ETHERNET CONTROL REGISTER 2
R/W-1 R/W-0
(1)
R/W-0 U-0 U-0 U-0 U-0 U-0
AUTOINC PKTDEC ETHEN — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 AUTOINC: Automatic Buffer Pointer Increment Enable bit
1 = Automatically increment ERDPT or EWRPT registers on reading from, or writing to, EDATA
0 = Do not automatically change ERDPT and EWRPT registers after EDATA is accessed
bit 6 PKTDEC: Packet Decrement bit
(1)
1 = Decrement the EPKTCNT register by one
0 = Leave EPKTCNT unchanged
bit 5 ETHEN: Ethernet Module Enable bit
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 4-0 Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared once it is set.
REGISTER 19-3: ESTAT: ETHERNET STATUS REGISTER
U-0 R/C-0 U-0 R/C-0 U-0 R-0 R/C-0 R-0
—BUFER— r — RXBUSY TXABRT PHYRDY
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 BUFER: Ethernet Buffer Error Status bit
1 = An Ethernet read or write has generated a buffer error (overrun or underrun)
0 = No buffer error has occurred
bit 5 Unimplemented: Read as ‘0’
bit 4 Reserved: Write as ‘0’
bit 3 Unimplemented: Read as ‘0’
bit 2 RXBUSY: Receive Busy bit
1 = Receive logic is receiving a data packet
0 = Receive logic is Idle
bit 1 TXABRT: Transmit Abort Error bit
1 = The transmit request was aborted
0 = No transmit abort error
bit 0 PHYRDY: Ethernet PHY Clock Ready bit
1 = Ethernet PHY start-up timer has expired; PHY is ready
0 = Ethernet PHY start-up timer is still counting; PHY is not ready