Datasheet

 2011 Microchip Technology Inc. DS39762F-page 217
PIC18F97J60 FAMILY
19.0 ETHERNET MODULE
All members of the PIC18F97J60 family of devices
feature an embedded Ethernet controller module. This
is a complete connectivity solution, including full imple-
mentations of both Media Access Control (MAC) and
Physical Layer (PHY) transceiver modules. Two pulse
transformers and a few passive components are all that
are required to connect the microcontroller directly to
an Ethernet network.
The Ethernet module meets all of the IEEE 802.3™
specifications for 10-BaseT connectivity to a twisted-pair
network. It incorporates a number of packet filtering
schemes to limit incoming packets. It also provides an
internal DMA module for fast data throughput and hard-
ware assisted IP checksum calculations. Provisions are
also made for two LED outputs to indicate link and
network activity.
A simple block diagram of the module is shown in
Figure 19-1.
The Ethernet module consists of five major functional
blocks:
1. The PHY transceiver module that encodes and
decodes the analog data that is present on the
twisted-pair interface and sends or receives it
over the network.
2. The MAC module that implements IEEE 802.3
compliant MAC logic and provides Media
Independent Interface Management (MIIM) to
control the PHY.
3. An independent, 8-Kbyte RAM buffer for storing
packets that have been received and packets
that are to be transmitted.
4. An arbiter to control access to the RAM buffer
when requests are made from the microcontroller
core, DMA, transmit and receive blocks.
5. The register interface that functions as an inter-
preter of commands and internal status signals
between the module and the microcontroller’s
SFRs.
FIGURE 19-1: ETHERNET MODULE BLOCK DIAGRAM
DMA and
IP Checksum
TXBM
RXBM
Arbiter
Flow Control
Host Interface
PHY
MII
Interface
MIIM
Interface
TPOUT+
TPOUT-
TPIN+
TPIN-
TX
RX
RBIAS
RXF (Filter)
RX
TX
MAC
ch0
ch1
ch0
ch1
Ethernet RAM
Buffer
EDATA
Ethernet
Control
Ethernet
Buffer Pointers
MIRD/MIWR
MIREGADR
PHY Register Data
PHY Register Addresses
Ethernet
Data
Ethernet
Buffer
Addresses
Microcontroller SFRs
Microcontroller Data Bus
LEDA/LEDB Control
8
8-Kbyte
ch2