Datasheet

 2011 Microchip Technology Inc. DS39762F-page 215
PIC18F97J60 FAMILY
TABLE 18-5: REGISTERS ASSOCIATED WITH ECCPx MODULES AND TIMER1 TO TIMER4
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
RCON IPEN
— CM RI TO PD POR BOR 70
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71
IPR1
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71
PIR2
OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71
PIE2
OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE 71
IPR2
OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP 71
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 71
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71
TRISD
(1)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71
TRISE TRISE7
(2)
TRISE6
(2)
TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71
TRISG
TRISG7 TRISG6 TRISG5 TRISG4 TRISG3
(2)
TRISG2 TRISG1 TRISG0
(2)
71
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71
TMR1L Timer1 Register Low Byte 70
TMR1H Timer1 Register High Byte 70
T1CON RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70
TMR2 Timer2 Register 70
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70
PR2 Timer2 Period Register 70
TMR3L Timer3 Register Low Byte 70
TMR3H Timer3 Register High Byte 70
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 71
TMR4 Timer4 Register 72
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 72
PR4 Timer4 Period Register 72
CCPRxL
(3)
Capture/Compare/PWM Register x Low Byte 70
CCPRxH
(3)
Capture/Compare/PWM Register x High Byte 70
CCPxCON
(3)
PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 70
ECCPxAS
(3)
ECCPXASE ECCPXAS2 ECCPXAS1 ECCPXAS0 PSSXAC1 PSSXAC0 PSSXBD1 PSSXBD0 70, 73
ECCPxDEL
(3)
PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 73
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used during ECCPx operation.
Note 1: Applicable in 64-pin devices only.
2: Registers and/or specific bits are unimplemented in 64-pin devices.
3: Generic term for all of the identical registers of this name for all Enhanced CCPx modules, where ‘x’ identifies the individual
module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same generic name are
identical.