Datasheet

 2011 Microchip Technology Inc. DS39762F-page 179
PIC18F97J60 FAMILY
EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71
TMR1L Timer1 Register Low Byte 70
TMR1H Timer1 Register High Byte 70
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 70
Legend: Shaded cells are not used by the Timer1 module.
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF
PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
; Insert the next 4 lines of code when TMR1
; can not be reliably updated before clock pulse goes low
BTFSC TMR1L,0 ; wait for TMR1L to become clear
BRA $-2 ; (may already be clear)
BTFSS TMR1L,0 ; wait for TMR1L to become set
BRA $-2 ; TMR1 has just incremented
; If TMR1 update can be completed before clock pulse goes low
; Start ISR here
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF
PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done