Datasheet

PIC18F97J60 FAMILY
DS39762F-page 170  2011 Microchip Technology Inc.
FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 72
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 72
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 72
LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 72
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71
PSPCON IBF OBF IBOV PSPMODE — — — — 71
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69
PIR1 PSPIF
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>