Datasheet

PIC18F97J60 FAMILY
DS39762F-page 166  2011 Microchip Technology Inc.
11.10 PORTJ, TRISJ and
LATJ Registers
PORTJ is implemented as a bidirectional port in two
different ways:
• 80-pin devices: 2 bits wide (RJ<5:4>)
• 100-pin devices: 8 bits wide (RJ<7:0>)
The corresponding Data Direction register is TRISJ.
Setting a TRISJ bit (= 1) will make the corresponding
PORTJ pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISJ
bit (= 0) will make the corresponding PORTJ pin an out-
put (i.e., put the contents of the output latch on the
selected pin). All pins on PORTJ are digital only and
tolerate voltages up to 5.5V.
The Output Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register read and write the latched output value for
PORTJ.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the
interface. This occurs automatically when the interface
is enabled by clearing the EBDIS control bit
(MEMCON<7>). The TRISJ bits are also overridden.
Each of the PORTJ pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by setting bit, RJPU (PORTA<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
EXAMPLE 11-9: INITIALIZING PORTJ
Note: PORTJ is available only on 80-pin and
100-pin devices.
Note: These pins are configured as digital inputs
on any device Reset.
CLRF PORTJ ; Initialize PORTG by
; clearing output
; data latches
CLRF LATJ ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISJ ; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs