Datasheet

 2011 Microchip Technology Inc. DS39762F-page 165
PIC18F97J60 FAMILY
TABLE 11-17: PORTH FUNCTIONS
TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RH0/A16 RH0 0 O DIG LATH<0> data output.
1 I ST PORTH<0> data input.
A16
(1)
x O DIG External memory interface, Address Line 16. Takes priority over port data.
RH1/A17 RH1 0 O DIG LATH<1> data output.
1 I ST PORTH<1> data input.
A17
(1)
x O DIG External memory interface, Address Line 17. Takes priority over port data.
RH2/A18 RH2 0 O DIG LATH<2> data output.
1 I ST PORTH<2> data input.
A18
(1)
x O DIG External memory interface, Address Line 18. Takes priority over port data.
RH3/A19 RH3 0 O DIG LATH<3> data output.
1 I ST PORTH<3> data input.
A19
(1)
x O DIG External memory interface, Address Line 19. Takes priority over port data.
RH4/AN12/P3C RH4 0 O DIG LATH<4> data output.
1 I ST PORTH<4> data input.
AN12 I ANA A/D Input Channel 12. Default input configuration on POR; does not affect
digital output.
P3C
(2)
0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH5/AN13/P3B RH5 0 O DIG LATH<5> data output.
1 I ST PORTH<5> data input.
AN13 I ANA A/D Input Channel 13. Default input configuration on POR; does not affect
digital output.
P3B
(2)
0 O DIG ECCP3 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH6/AN14/P1C RH6 0 O DIG LATH<6> data output.
1 I ST PORTH<6> data input.
AN14 I ANA A/D Input Channel 14. Default input configuration on POR; does not affect
digital output.
P1C
(2)
0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RH7/AN15/P1B RH7 0 O DIG LATH<7> data output.
1 I ST PORTH<7> data input.
AN15 I ANA A/D Input Channel 15. Default input configuration on POR; does not affect
digital output.
P1B
(2)
0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Unimplemented on 80-pin devices.
2: Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared (80-pin and 100-pin
devices only). Default assignments are PORTE<6:3>.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 72
LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 71
TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71