Datasheet

 2011 Microchip Technology Inc. DS39762F-page 163
PIC18F97J60 FAMILY
TABLE 11-15: PORTG FUNCTIONS
TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/ECCP3/
P3A
(1)
RG0
(1)
0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
ECCP3
(1)
0 O DIG ECCP3 compare and PWM output; takes priority over port data.
1 I ST ECCP3 capture input.
P3A
(1)
0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RG1/TX2/
CK2
(1)
RG1
(1)
0 O DIG LATG<1> data output.
1 I ST PORTG<1> data input.
TX2
(1)
1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data.
CK2
(1)
1 O DIG Synchronous serial data input (EUSART2 module). User must configure as an input.
1 I ST Synchronous serial clock input (EUSART2 module).
RG2/RX2/
DT2
(1)
RG2
(1)
0 O DIG LATG<2> data output.
1 I ST PORTG<2> data input.
RX2
(1)
1 I ST Asynchronous serial receive data input (EUSART2 module).
DT2
(1)
1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data.
1 I ST Synchronous serial data input (EUSART2 module). User must configure as an input.
RG3/CCP4/
P3D
(1)
RG3
(1)
0 O DIG LATG<3> data output.
1 I ST PORTG<3> data input.
CCP4
(1)
0 O DIG CCP4 compare output and PWM output; takes priority over port data.
1 I ST CCP4 capture input.
P3D
(1)
0 O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RG4/CCP5/
P1D
RG4 0 O DIG LATG<4> data output.
1 I ST PORTG<4> data input.
CCP5 0 O DIG CCP5 compare output and PWM output; takes priority over port data.
1 I ST CCP5 capture input.
P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RG5
(2)
RG5
(2)
0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
RG6
(2)
RG6
(2)
0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
RG7
(2)
RG7
(2)
0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Implemented on 80-pin and 100-pin devices only.
2: Implemented on 100-pin devices only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page:
PORTG RG7
(1)
RG6
(1)
RG5
(1)
RG4 RG3
(2)
RG2
(2)
RG1
(2)
RG0
(2)
72
LATG LATG7
(1)
LATG6
(1)
LATG5
(1)
LATG4 LATG3
(2)
LATG2
(2)
LATG1
(2)
LATG0
(2)
72
TRISG TRISG7
(1)
TRISG6
(1)
TRISG5
(1)
TRISG4 TRISG3
(2)
TRISG2
(2)
TRISG1
(2)
TRISG0
(2)
71
Note 1: Implemented on 100-pin devices only.
2: Implemented on 80-pin and 100-pin devices only.