Datasheet

PIC18F97J60 FAMILY
DS39762F-page 16  2011 Microchip Technology Inc.
FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
8
8
3
W
8
8
8
Instruction
Decode &
Control
State Machine
Control Signals
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA5
(1)
RC0:RC7
(1)
RD0:RD2
(1)
RE0:RE7
(1)
RF1:RF7
(1)
RG0:RG4
(1)
PORTB
RB0:RB7
(1)
PORTH
RH0:RH7
(1)
PORTJ
RJ4:RJ5
(1)
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
ADC
10-Bit
EUSART2
ECCP2 ECCP3
CCP4 CCP5
Timer4
Note 1: See Ta ble 1- 5 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Data Latch
Data Memory
(3808 Bytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
20
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
PCLATU
PCU
Instruction Bus <16>
STKPTR
Bank
Decode
ROM Latch
Ethernet
Address Latch
Program Memory
(64, 96, 128 Kbytes)
Data Latch