Datasheet

 2011 Microchip Technology Inc. DS39762F-page 159
PIC18F97J60 FAMILY
TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
RE5/AD13/
P1C
RE5 0 O DIG LATE<5> data output.
1 I ST PORTE<5> data input; weak pull-up when REPU bit is set.
AD13
(1)
x O DIG External memory interface, Address/Data Bit 13 output.
(2)
x I TTL External memory interface, Data Bit 13 input.
(2)
P1C
(3)
0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE6/AD14/
P1B
(4)
RE6 0 O DIG LATE<6> data output.
1 I ST PORTE<6> data input; weak pull-up when REPU bit is set.
AD14
(1)
x O DIG External memory interface, Address/Data Bit 14 output.
(2)
x I TTL External memory interface, Data Bit 14 input.
(2)
P1B
(3)
0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7/AD15/
ECCP2/P2A
(4)
RE7 0 O DIG LATE<7> data output.
1 I ST PORTE<7> data input; weak pull-up when REPU bit is set.
AD15
(1)
x O DIG External memory interface, Address/Data Bit 15 output.
(2)
x I TTL External memory interface, Data Bit 15 input.
(2)
ECCP2
(5)
0 O DIG ECCP2 compare output and PWM output; takes priority over
port data.
1 I ST ECCP2 capture input.
P2A
(5)
0 O DIG ECCP2 Enhanced PWM output, Channel A; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
PORTE RE7
(1)
RE6
(1)
RE5 RE4 RE3 RE2 RE1 RE0 72
LATE LATE7
(1)
LATE6
(1)
LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 72
TRISE TRISE7
(1)
TRISE6
(1)
TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71
LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 72
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices; read as ‘0’.
TABLE 11-11: PORTE FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: EMB functions are implemented on 100-pin devices only.
2: External memory interface I/O takes priority over all other digital and PSP I/O.
3: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices).
4: Unimplemented on 64-pin devices.
5: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in
Microcontroller mode).
6: Unimplemented on 64-pin and 80-pin devices.