Datasheet

PIC18F97J60 FAMILY
DS39762F-page 158  2011 Microchip Technology Inc.
TABLE 11-11: PORTE FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AD8/RD
/
P2D
RE0 0 O DIG LATE<0> data output.
1 I ST PORTE<0> data input; weak pull-up when REPU bit is set.
AD8
(1)
x O DIG External memory interface, Address/Data Bit 8 output.
(2)
x I TTL External memory interface, Data bit 8 input.
(2)
RD
(6)
1 I TTL Parallel Slave Port read enable control input.
P2D 0 O DIG ECCP2 Enhanced PWM output, Channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/WR
/
P2C
RE1 0 O DIG LATE<1> data output.
1 I ST PORTE<1> data input; weak pull-up when REPU bit is set.
AD9
(1)
x O DIG External memory interface, Address/Data Bit 9 output.
(2)
x I TTL External memory interface, Data Bit 9 input.
(2)
WR
(6)
1 I TTL Parallel Slave Port write enable control input.
P2C 0 O DIG ECCP2 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/CS
/
P2B
RE2 0 O DIG LATE<2> data output.
1 I ST PORTE<2> data input; weak pull-up when REPU bit is set.
AD10
(1)
x O DIG External memory interface, Address/Data Bit 10 output.
(2)
x I TTL External memory interface, Data Bit 10 input.
(2)
CS
(6)
1 I TTL Parallel Slave Port chip select control input.
P2B 0 O DIG ECCP2 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
P3C
RE3 0 O DIG LATE<3> data output.
1 I ST PORTE<3> data input; weak pull-up when REPU bit is set.
AD11
(1)
x O DIG External memory interface, Address/Data Bit 11 output.
(2)
x I TTL External memory interface, Data Bit 11 input.
(2)
P3C
(3)
0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE4/AD12/
P3B
RE4 0 O DIG LATE<4> data output.
1 I ST PORTE<4> data input; weak pull-up when REPU bit is set.
AD12
(1)
x O DIG External memory interface, Address/Data Bit 12 output.
(2)
x I TTL External memory interface, Data Bit 12 input.
(2)
P3B
(3)
0 O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: EMB functions are implemented on 100-pin devices only.
2: External memory interface I/O takes priority over all other digital and PSP I/O.
3: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices).
4: Unimplemented on 64-pin devices.
5: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in
Microcontroller mode).
6: Unimplemented on 64-pin and 80-pin devices.