Datasheet

PIC18F97J60 FAMILY
DS39762F-page 156  2011 Microchip Technology Inc.
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
RD5/AD5/
PSP5/SDI2/
SDA2
(1)
RD5
(1)
0 O DIG LATD<5> data output.
1 I ST PORTD<5> data input; weak pull-up when RDPU bit is set.
AD5
(1)
x O DIG External memory interface, Address/Data Bit 5 output.
(2)
x I TTL External memory interface, Data Bit 5 input.
(2)
PSP5
(1)
x O DIG PSP read output data (LATD<5>); takes priority over port data.
x I TTL PSP write data input.
SDI2
(1)
1 I ST SPI data input (MSSP2 module).
SDA2
(1)
1 ODIGI
2
C™ data output (MSSP2 module); takes priority over port data.
1 ISTI
2
C data input (MSSP2 module); input type depends on module
setting.
RD6/AD6/
PSP6/SCK2/
SCL2
(1)
RD6
(1)
0 O DIG LATD<6> data output.
1 I ST PORTD<6> data input; weak pull-up when RDPU bit is set.
AD6
(1)
x O DIG-3 External memory interface, Address/Data Bit 6 output.
(2)
x I TTL External memory interface, Data Bit 6 input.
(2)
PSP6
(1)
x O DIG PSP read output data (LATD<6>); takes priority over port data.
x I TTL PSP write data input.
SCK2
(1)
0 O DIG SPI clock output (MSSP2 module); takes priority over port data.
1 I ST SPI clock input (MSSP2 module).
SCL2
(1)
0 ODIGI
2
C clock output (MSSP2 module); takes priority over port data.
1 ISTI
2
C clock input (MSSP2 module); input type depends on module
setting.
RD7/AD7/
PSP7/SS2
(1)
RD7
(1)
0 O DIG LATD<7> data output.
1 I ST PORTD<7> data input; weak pull-up when RDPU bit is set.
AD7
(1)
x O DIG External memory interface, Address/Data Bit 7 output.
(2)
x I TTL External memory interface, Data Bit 7 input.
(2)
PSP7
(1)
x O DIG PSP read output data (LATD<7>); takes priority over port data.
x I TTL PSP write data input.
SS2
(1)
x I TTL Slave select input for MSSP2 module.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
PORTD RD7
(1)
RD6
(1)
RD5
(1)
RD4
(1)
RD3
(1)
RD2 RD1 RD0 72
LATD LATD7
(1)
LATD6
(1)
LATD5
(1)
LATD4
(1)
LATD3
(1)
LATD2 LATD1 LATD0 72
TRISD TRISD7
(1)
TRISD6
(1)
TRISD5
(1)
TRISD4
(1)
TRISD3
(1)
TRISD2 TRISD1 TRISD0 71
LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 72
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin and 80-pin devices; read as ‘0’.
TABLE 11-9: PORTD FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: These features or port pins are implemented only on 100-pin devices.
2: External memory interface I/O takes priority over all other digital and PSP I/O.
3: These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with
RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).