Datasheet

 2011 Microchip Technology Inc. DS39762F-page 155
PIC18F97J60 FAMILY
TABLE 11-9: PORTD FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/AD0/PSP0
(RD0/P1B)
RD0 0 O DIG LATD<0> data output.
1 I ST PORTD<0> data input; weak pull-up when RDPU bit is set.
AD0
(1)
x O DIG External memory interface, Address/Data Bit 0 output.
(2)
x I TTL External memory interface, Data Bit 0 input.
(2)
PSP0
(1)
x O DIG PSP read output data (LATD<0>); takes priority over port data.
x I TTL PSP write data input.
P1B
(3)
0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD1/AD1/PSP1
(RD1/ECCP3/
P3A)
RD1 0 O DIG LATD<1> data output.
1 I ST PORTD<1> data input; weak pull-up when RDPU bit is set.
AD1
(1)
x O DIG External memory interface, Address/Data Bit 1 output.
(2)
x I TTL External memory interface, Data Bit 1 input.
(2)
PSP1
(1)
x O DIG PSP read output data (LATD<1>); takes priority over port data.
x I TTL PSP write data input.
ECCP3
(3)
0 O DIG ECCP3 compare and PWM output; takes priority over port data.
1 I ST ECCP3 capture input.
P3A
(3)
0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD2/AD2/PSP2
(RD2/CCP4/
P3D)
RD2 0 O DIG LATD<2> data output.
1 I ST PORTD<2> data input; weak pull-up when RDPU bit is set.
AD2
(1)
x O DIG External memory interface, Address/Data Bit 2 output.
(2)
x I TTL External memory interface, Data Bit 2 input.
(2)
PSP2
(1)
x O DIG PSP read output data (LATD<2>); takes priority over port data.
x I TTL PSP write data input.
CCP4
(3)
0 O DIG CCP4 compare output and PWM output; takes priority over port data.
1 I ST CCP4 capture input.
P3D
(3)
0 O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD3/AD3/
PSP3
(1)
RD3
(1)
0 O DIG LATD<3> data output.
1 I ST PORTD<3> data input; weak pull-up when RDPU bit is set.
AD3
(1)
x O DIG External memory interface, Address/Data Bit 3 output.
(2)
x I TTL External memory interface, Data Bit 3 input.
(2)
PSP3
(1)
x O DIG PSP read output data (LATD<3>); takes priority over port data.
x I TTL PSP write data input.
RD4/AD4/
PSP4/SDO2
(1)
RD4
(1)
0 O DIG LATD<4> data output.
1 I ST PORTD<4> data input; weak pull-up when RDPU bit is set.
AD4
(1)
x O DIG External memory interface, Address/Data Bit 4 output.
(2)
x I TTL External memory interface, Data Bit 4 input.
(2)
PSP4
(1)
x O DIG PSP read output data (LATD<4>); takes priority over port data.
x I TTL PSP write data input.
SDO2
(1)
0 O DIG SPI data output (MSSP2 module); takes priority over port data.
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: These features or port pins are implemented only on 100-pin devices.
2: External memory interface I/O takes priority over all other digital and PSP I/O.
3: These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with
RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D).