Datasheet

PIC18F97J60 FAMILY
DS39762F-page 152  2011 Microchip Technology Inc.
TABLE 11-7: PORTC FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RC0/T1OSO/
T13CKI
RC0 0 O DIG LATC<0> data output.
1 I ST PORTC<0> data input.
T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator is enabled.
Disables digital I/O.
T13CKI 1 I ST Timer1/Timer3 counter input.
RC1/T1OSI/
ECCP2/P2A
RC1 0 O DIG LATC<1> data output.
1 I ST PORTC<1> data input.
T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables
digital I/O.
ECCP2
(1)
0 O DIG ECCP2 compare output and PWM output; takes priority over port data.
1 I ST ECCP2 capture input.
P2A
(1)
0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC2/ECCP1/
P1A
RC2 0 O DIG LATC<2> data output.
1 I ST PORTC<2> data input.
ECCP1 0 O DIG ECCP1 compare output and PWM output; takes priority over port data.
1 I ST ECCP1 capture input.
P1A 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RC3/SCK1/
SCL1
RC3 0 O DIG LATC<3> data output.
1 I ST PORTC<3> data input.
SCK1 0 O DIG SPI clock output (MSSP1 module); takes priority over port data.
1 I ST SPI clock input (MSSP1 module).
SCL1 0 ODIGI
2
C™ clock output (MSSP1 module); takes priority over port data.
1 ISTI
2
C clock input (MSSP1 module); input type depends on module setting.
RC4/SDI1/
SDA1
RC4 0 O DIG LATC<4> data output.
1 I ST PORTC<4> data input.
SDI1 1 I ST SPI data input (MSSP1 module).
SDA1 1 ODIGI
2
C data output (MSSP1 module); takes priority over port data.
1 ISTI
2
C data input (MSSP1 module); input type depends on module setting.
RC5/SDO1 RC5 0 O DIG LATC<5> data output.
1 I ST PORTC<5> data input.
SDO1 0 O DIG SPI data output (MSSP1 module); takes priority over port data.
RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output.
1 I ST PORTC<6> data input.
TX1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data.
CK1 1 O DIG Synchronous serial data input (EUSART1 module). User must configure as
an input.
1 I ST Synchronous serial clock input (EUSART1 module).
RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output.
1 I ST PORTC<7> data input.
RX1 1 I ST Asynchronous serial receive data input (EUSART1 module).
DT1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over
port data.
1 I ST Synchronous serial data input (EUSART1 module). User must configure as
an input.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.