Datasheet

 2011 Microchip Technology Inc. DS39762F-page 139
PIC18F97J60 FAMILY
REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
SSP2IE
(1)
BCL2IE
(1)
RC2IE
(2)
TX2IE
(2)
TMR4IE CCP5IE CCP4IE CCP3IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SSP2IE: MSSP2 Interrupt Enable bit
(1)
1 = Enabled
0 =Disabled
bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
(1)
1 = Enabled
0 =Disabled
bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit
(2)
1 = Enabled
0 =Disabled
bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit
(2)
1 = Enabled
0 =Disabled
bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 2 CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 1 CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 0 CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 =Disabled
Note 1: Implemented in 100-pin devices only.
2: Implemented in 80-pin and 100-pin devices only.