Datasheet

PIC18F97J60 FAMILY
DS39762F-page 138  2011 Microchip Technology Inc.
REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
OSCFIE CMIE ETHIE rBCL1IE— TMR3IE CCP2IE
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 ETHIE: Ethernet Module Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 Reserved: Maintain as ‘0’
bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1 = Enabled
0 = Disabled
bit 2 Unimplemented: Read as ‘0’
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled