PIC18F97J60 Family Data Sheet 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F97J60 FAMILY 64/80/100-Pin High-Performance, 1-Mbit Flash Microcontrollers with Ethernet Ethernet Features: Peripheral Highlights: • • • • • • • • • High-Current Sink/Source: 25 mA/25 mA on PORTB and PORTC • Five Timer modules (Timer0 to Timer4) • Four External Interrupt pins • Two Capture/Compare/PWM (CCP) modules • Three Enhanced Capture/Compare/PWM (ECCP) modules: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart • Up to Two Master Syn
Comparators PIC18F66J60 64K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F66J65 96K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F67J60 128K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F86J60 64K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F86J65 96K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F87J60 128K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F96J60 64K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y PIC18F96J65 9
PIC18F97J60 FAMILY VDDTX TPOUT- TPOUT+ VSSTX RBIAS VDDPLL VSSPLL VSS VDD RD2/CCP4/P3D RD0/P1B RE5/P1C RE4/P3B RE3/P3C RE2/P2B 64-Pin TQFP RD1/ECCP3/P3A Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/P2C 1 48 RE0/P2D 2 RB0/INT0/FLT0 RB1/INT1 RB2/INT2 3 4 5 47 46 45 RB3/INT3 MCLR RG4/CCP5/P1D 6 VSS VDDCORE/VCAP RF7/SS1 7 8 9 RF4/AN9 10 11 12 13 14 RF3/AN8 RF2/AN7/C1OUT 15 16 RF6/AN11 RF5/AN10/CVREF 44 43 42 41 40 PIC18F66J60 PIC18F66J65 PIC18F67J60 39 3
PIC18F97J60 FAMILY Pin Diagrams (Continued) VDDTX TPOUT+ TPOUT- VSSTX RBIAS VDDPLL VSSPLL RD2 RD1 VSS VDD RE7/ECCP2(1)/P2A(1) RD0 RE6/P1B(2) RE5/P1C(2) RE4/P3B(2) RE3/P3C(2) RE2/P2B RH0 RH1 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2 1 60 VDDRX RH3 2 RE1/P2C RE0/P2D 3 4 5 6 7 59 58 57 56 55 TPIN+ TPINVSSRX RG0/ECCP3/P3A RG1/TX2/CK2 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC VSS OSC2/CLKO OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO1 RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3
PIC18F97J60 FAMILY Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RH1/A17 RH0/A16 RE2/AD10/CS/P2B RE3/AD11/P3C(2) RE4/AD12/P3B(2) RE5/AD13/P1C(2) RE6/AD14/P1B(2) RE7/AD15/ECCP2(1)/P2A(1) RD0/AD0/PSP0 RD1/AD1/PSP1 RD2/AD2/PSP2 RD3/AD3/PSP3 RD4/AD4/PSP4/SDO2 RD5/AD5/PSP5/SDI2/SDA2 VDD VSS RD6/AD6/PSP6/SCK2/SCL2 RD7/AD7/PSP7/SS2 VSSPLL VDDPLL RBIAS VSSTX TPOUT+ TPOUTVDDTX 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PI
PIC18F97J60 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 43 3.0 Oscillator Configurations .....................................................................................
PIC18F97J60 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18F97J60 FAMILY NOTES: DS39762F-page 10 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F66J60 • PIC18F87J60 • PIC18F66J65 • PIC18F96J60 • PIC18F67J60 • PIC18F96J65 • PIC18F86J60 • PIC18F97J60 • PIC18F86J65 This family introduces a new line of low-voltage devices with the foremost traditional advantage of all PIC18 microcontrollers – namely, high computational performance and a rich feature set at an extremely competitive price point.
PIC18F97J60 FAMILY 1.2 Other Special Features • Communications: The PIC18F97J60 family incorporates a range of serial communication peripherals, including up to two independent Enhanced USARTs and up to two Master SSP modules, capable of both SPI and I2C™ (Master and Slave) modes of operation. In addition, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications.
PIC18F97J60 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC18F66J60 PIC18F66J65 PIC18F67J60 DC – 41.667 MHz DC – 41.667 MHz DC – 41.
PIC18F97J60 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (100-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources PIC18F96J60 PIC18F96J65 PIC18F97J60 DC – 41.667 MHz DC – 41.667 MHz DC – 41.
PIC18F97J60 FAMILY FIGURE 1-1: PIC18F66J60/66J65/67J60 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch STKPTR Program Memory (64, 96, 128 Kbytes) PORTB RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 12 Data Latch 8 RA0:RA5(1) Data Memory (3808 Bytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic PORTC RC0:RC7(1) inc/dec logic Table Latch Address Decode ROM Latch Instructio
PIC18F97J60 FAMILY FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 31 Level Stack 4 BSR STKPTR 12 FSR0 FSR1 FSR2 RB0:RB7(1) 4 Access Bank PORTC RC0:RC7(1) 12 Data Latch 8 PORTB 12 Data Address<12> Address Latch Program Memory (64, 96, 128 Kbytes) RA0:RA5(1) Data Memory (3808 Bytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic inc/dec logic Table Latch PORTD RD0:RD2(1) Address Decode ROM
PIC18F97J60 FAMILY FIGURE 1-3: PIC18F96J60/96J65/97J60 (100-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 21 Address Latch PCU PCH PCL Program Counter System Bus Interface 31 Level Stack STKPTR PORTB 12 Data Address<12> 4 Address Latch Program Memory (64, 96, 128 Kbytes) RA0:RA5(1) Data Memory (3808 Bytes) PCLATU PCLATH 20 PORTA Data Latch 8 8 4 12 BSR RB0:RB7(1) PORTC Access Bank FSR0 FSR1 FSR2 RC0:RC7(1) 12 Data Latch inc/dec logic 8 Table Latch PORTD RD0:RD7(1
PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 7 I ST OSC1/CLKI OSC1 39 Pin Name I CLKI I OSC2/CLKO OSC2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function, OSC1.
PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port.
PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/P1B RD0 P1B 60 RD1/ECCP3/P3A RD1 ECCP3 P3A 59 RD2/CCP4/P3D RD2 CCP4 P3D 58 Legend: TTL ST I P = = = = I/O O ST — Digital I/O. ECCP1 PWM Output B. I/O I/O O ST ST — Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A. I/O I/O O ST ST — Digital I/O.
PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/P2D RE0 P2D 2 RE1/P2C RE1 P2C 1 RE2/P2B RE2 P2B 64 RE3/P3C RE3 P3C 63 RE4/P3B RE4 P3B 62 RE5/P1C RE5 P1C 61 Legend: TTL ST I P = = = = DS39762F-page 22 I/O O ST — Digital I/O. ECCP2 PWM Output D. I/O O ST — Digital I/O. ECCP2 PWM Output C. I/O O ST — Digital I/O. ECCP2 PWM Output B.
PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF3 AN8 15 RF4/AN9 RF4 AN9 14 RF5/AN10/CVREF RF5 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS1 RF7 SS1 11 Legend: TTL ST I P = = = = I/O I O ST Analog — Digital I/O. Analog Input 6. Comparator 2 output.
PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. 8 RG4/CCP5/P1D RG4 CCP5 P1D I/O I/O O ST ST — Digital I/O. Capture 5 input/Compare 5 output/PWM5 output. ECCP1 PWM Output D. VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 9 I ST OSC1/CLKI OSC1 49 Pin Name I CLKI I OSC2/CLKO OSC2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function, OSC1.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0 72 I/O ST Digital I/O. RD1 69 I/O ST Digital I/O. RD2 68 I/O ST Digital I/O. PORTE is a bidirectional I/O port.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT RF1 AN6 C2OUT 23 RF2/AN7/C1OUT RF2 AN7 C1OUT 18 RF3/AN8 RF3 AN8 17 RF4/AN9 RF4 AN9 16 RF5/AN10/CVREF RF5 AN10 CVREF 15 RF6/AN11 RF6 AN11 14 RF7/SS1 RF7 SS1 13 Legend: Note 1: 2: 3: 4: I/O I O ST Analog — Digital I/O. Analog Input 6. Comparator 2 output. I/O I O ST Analog — Digital I/O.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 P3A 56 RG1/TX2/CK2 RG1 TX2 CK2 55 RG2/RX2/DT2 RG2 RX2 DT2 42 RG3/CCP4/P3D RG3 CCP4 P3D 41 RG4/CCP5/P1D RG4 CCP5 P1D 10 Legend: Note 1: 2: 3: 4: I/O I/O O ST ST — Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A. I/O O I/O ST — ST Digital I/O.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0 79 I/O ST Digital I/O. RH1 80 I/O ST Digital I/O. RH2 1 I/O ST Digital I/O. RH3 2 I/O ST Digital I/O. RH4/AN12/P3C RH4 AN12 P3C(4) 22 I/O I O ST Analog — Digital I/O. Analog Input 12. ECCP3 PWM Output C. RH5/AN13/P3B RH5 AN13 P3B(4) 21 I/O I O ST Analog — Digital I/O. Analog Input 13.
PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ4 39 I/O ST RJ5 40 I/O ST VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins. VDD 32, 48, 71 P — Positive supply for peripheral digital logic and I/O pins. AVSS 26 P — Ground reference for analog modules. AVDD 25 P — Positive supply for analog modules.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 13 I ST OSC1/CLKI OSC1 63 Pin Name I CLKI I OSC2/CLKO OSC2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function, OSC1.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 12 RF1/AN6/C2OUT RF1 AN6 C2OUT 28 RF2/AN7/C1OUT RF2 AN7 C1OUT 23 RF3/AN8 RF3 AN8 22 RF4/AN9 RF4 AN9 21 RF5/AN10/CVREF RF5 AN10 CVREF 20 RF6/AN11 RF6 AN11 19 RF7/SS1 RF7 SS1 18 Legend: Note 1: 2: 3: 4: 5: I/O I ST Analog Digital I/O. Analog Input 5. I/O I O ST Analog — Digital I/O.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 P3A 71 RG1/TX2/CK2 RG1 TX2 CK2 70 RG2/RX2/DT2 RG2 RX2 DT2 52 RG3/CCP4/P3D RG3 CCP4 P3D 51 RG4/CCP5/P1D RG4 CCP5 P1D 14 I/O I/O O ST ST — Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A. I/O O I/O ST — ST Digital I/O. EUSART2 asynchronous transmit.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0/A16 RH0 A16 99 RH1/A17 RH1 A17 100 RH2/A18 RH2 A18 1 RH3/A19 RH3 A19 2 RH4/AN12/P3C RH4 AN12 P3C(5) 27 RH5/AN13/P3B RH5 AN13 P3B(5) 26 RH6/AN14/P1C RH6 AN14 P1C(5) 25 RH7/AN15/P1B RH7 AN15 P1B(5) 24 Legend: Note 1: 2: 3: 4: 5: I/O O ST — Digital I/O. External Memory Address 16.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 49 RJ1/OE RJ1 OE 50 RJ2/WRL RJ2 WRL 66 RJ3/WRH RJ3 WRH 61 RJ4/BA0 RJ4 BA0 47 RJ5/CE RJ5 CE 48 RJ6/LB RJ6 LB 58 RJ7/UB RJ7 UB 39 Legend: Note 1: 2: 3: 4: 5: I/O O ST — Digital I/O. External memory address latch enable. I/O O ST — Digital I/O. External memory output enable.
PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type NC 9 — — No connect. VSS 15, 36, 40, 60, 65, 85 P — Ground reference for logic and I/O pins. VDD 17, 37, 59, 62, 86 P — Positive supply for peripheral digital logic and I/O pins. AVSS 31 P — Ground reference for analog modules. AVDD 30 P — Positive supply for analog modules. ENVREG 29 I ST Enable for on-chip voltage regulator.
PIC18F97J60 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section 2.
PIC18F97J60 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F97J60 FAMILY 2.4 Voltage Regulator Pins (ENVREG and VCAP/VDDCORE) The on-chip voltage regulator enable pin, ENVREG, must always be connected directly to either a supply voltage or to ground. Tying ENVREG to VDD enables the regulator, while tying it to ground disables the regulator. Refer to Section 25.3 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. Note that the “LF” versions of some low pin count PIC18FJ parts (e.g.
PIC18F97J60 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the VDDCORE voltage regulator of this microcontroller.
PIC18F97J60 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC18F97J60 FAMILY NOTES: DS39762F-page 48 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 3.0 3.1 OSCILLATOR CONFIGURATIONS 3.2 Overview 1. 2. HS HSPLL 3. 4. EC ECPLL 5. INTRC Oscillator Types The PIC18F97J60 family of devices can be operated in five different oscillator modes: Devices in the PIC18F97J60 family incorporate an oscillator and microcontroller clock system that differs from standard PIC18FXXJXX devices.
PIC18F97J60 FAMILY 3.3 Crystal Oscillator/Ceramic Resonators (HS Modes) In HS or HSPLL Oscillator modes, a crystal is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-2 shows the pin connections. Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
PIC18F97J60 FAMILY 3.5 Internal Oscillator Block The PIC18F97J60 family of devices includes an internal oscillator source (INTRC) which provides a nominal 31 kHz output. The INTRC is enabled on device power-up and clocks the device during its configuration cycle until it enters operating mode.
PIC18F97J60 FAMILY TABLE 3-2: DEVICE CLOCK SPEEDS FOR VARIOUS PLL BLOCK CONFIGURATIONS 5x PLL PLL Prescaler PLL Postscaler PLL Block Configuration (OSCTUNE<7:4>) Clock Frequency (MHz) Disabled x101 (Note 1) 2 1111 31.2500 3 0111 20.8333 2 Enabled Disabled Disabled x100 41.6667 3 2 1110 20.8333 3 0110 13.8889 Disabled(2) Disabled x00x 25 (Default) 2 1011 6.2500 3 0011 4.1667 2 1010 4.1667 3 0010 2.
PIC18F97J60 FAMILY 3.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<2:0> Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator.
PIC18F97J60 FAMILY 3.7.1.1 System Clock Selection and the FOSC2 Configuration Bit The SCS bits are cleared on all forms of Reset. In the device’s default configuration, this means the primary oscillator, defined by FOSC<1:0> (that is, one of the HC or EC modes), is used as the primary clock source on device Resets. The default clock configuration on Reset can be changed with the FOSC2 Configuration bit. This bit affects the clock source selection setting when SCS<1:0> = 00.
PIC18F97J60 FAMILY 4.0 4.1.1 POWER-MANAGED MODES CLOCK SOURCES The PIC18F97J60 family devices provide the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power.
PIC18F97J60 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In general, only one of these bits will be set while in a given power-managed mode.
PIC18F97J60 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 T1OSI Q2 1 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 4-2: PC + 2 PC + 4 TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed PC + 2 PC PC + 4 OSTS bit Se
PIC18F97J60 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18F97J60 FAMILY 4.3 Sleep Mode 4.4 The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC MCU devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate.
PIC18F97J60 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F97J60 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator. This mode allows for controllable power conservation during Idle periods. From RC_RUN mode, RC_IDLE mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP.
PIC18F97J60 FAMILY NOTES: DS39762F-page 62 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 5.0 RESET The PIC18F97J60 family of devices differentiates between various kinds of Reset: a) b) c) d) e) f) g) h) i) MCLR Reset during normal operation MCLR Reset during power-managed modes Power-on Reset (POR) Brown-out Reset (BOR) Configuration Mismatch (CM) RESET Instruction Stack Full Reset Stack Underflow Reset Watchdog Timer (WDT) Reset during execution This section discusses Resets generated by hard events (MCLR), power events (POR and BOR) and Configuration Mismatches (CM).
PIC18F97J60 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0
PIC18F97J60 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. 5.3 D(1) C POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a Power-on Reset occurs; it does not change for any other Reset event.
PIC18F97J60 FAMILY A CM Reset behaves similarly to a Master Clear Reset, RESET instruction, WDT time-out or Stack Event Reset. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. 5.6 Power-up Timer (PWRT) PIC18F97J60 family of devices incorporates an on-chip Power-up Timer (PWRT) to help regulate the Power-on Reset process. The PWRT is always enabled.
PIC18F97J60 FAMILY FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 5.7 TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table 5-1. These bits are used in software to determine the nature of the Reset. Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.
PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt TOSU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XJ6X PIC18F8XJ6X
PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt STATUS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6XJ6X PIC18F8
PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt T3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 uuuu uuuu uuuu uuuu PSPCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 ---- 0000 ---- uuuu ---- SPBRG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F6XJ6X PIC18
PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register LATG LATF Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x ---- ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt CCP4CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu CCPR5H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON PIC18F6XJ6X PI
PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt ETXNDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ETXNDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ETXSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ETXSTL PIC18F6XJ6X PIC1
PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt MAIPGH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MAIPGL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MABBIPG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MACON4 PIC18F6XJ6X PIC
PIC18F97J60 FAMILY NOTES: DS39762F-page 76 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY MEMORY ORGANIZATION There are two types of memory in PIC18 Flash microcontroller devices: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses. This allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 “Flash Program Memory”. FIGURE 6-1: 6.
PIC18F97J60 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. Because the PIC18F97J60 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information.
PIC18F97J60 FAMILY 6.1.3 PIC18F9XJ60/9XJ65 PROGRAM MEMORY MODES The 100-pin devices in this family can address up to a total of 2 Mbytes of program memory. This is achieved through the external memory bus. There are two distinct operating modes available to the controllers: • Microcontroller (MC) • Extended Microcontroller (EMC) The program memory mode is determined by setting the EMB Configuration bits (CONFIG3L<5:4>), as shown in Register 6-1. (Also see Section 25.
PIC18F97J60 FAMILY 6.1.4 EXTENDED MICROCONTROLLER MODE AND ADDRESS SHIFTING To avoid this, the Extended Microcontroller mode implements an address shifting option to enable automatic address translation. In this mode, addresses presented on the external bus are shifted down by the size of the on-chip program memory and are remapped to start at 0000h. This allows the complete use of the external memory device’s memory space.
PIC18F97J60 FAMILY 6.1.5 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F97J60 FAMILY 6.1.6.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop returns a value of zero to the PC, and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 6-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit.
PIC18F97J60 FAMILY 6.1.6.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 1L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
PIC18F97J60 FAMILY 6.2 6.2.2 PIC18 Instruction Cycle 6.2.1 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F97J60 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 6.1.5 “Program Counter”).
PIC18F97J60 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory is changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of addressable memory. The memory space is divided into 16 banks that contain 256 bytes each.
PIC18F97J60 FAMILY FIGURE 6-7: DATA MEMORY MAP FOR PIC18F97J60 FAMILY DEVICES When a = 0: BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h Bank 4 The remaining 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction.
PIC18F97J60 FAMILY FIGURE 6-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 11 From Opcode(2) 11 11 11 11 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR3:BSR0) to the registers of the Access Bank.
PIC18F97J60 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. The main group of SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh).
PIC18F97J60 FAMILY 6.3.5 ETHERNET SFRs Note: In addition to the standard SFR set in Bank 15, members of the PIC18F97J60 family have a second set of SFRs. This group, associated exclusively with the Ethernet module, occupies the top half of Bank 14 (E80h to EFFh). TABLE 6-4: To improve performance, frequently accessed Ethernet registers are located in the standard SFR bank (F60h through FFFh). A complete list of Ethernet SFRs is given in Table 6-4. All SFRs are fully described in Table 6-5.
PIC18F97J60 FAMILY TABLE 6-5: File Name TOSU REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) Bit 7 Bit 6 Bit 5 — — — Bit 4 Top-of-Stack Register High Byte (TOS<15:8>) TOSL Top-of-Stack Register Low Byte (TOS<7:0>) STKPTR STKFUL(1) STKUNF(1) — PCLATU — — bit 21(2) Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — — bit 21 Bit 2 Bit 1 Bit 0 Top-of-Stack Register Upper Byte (TOS<20:16>) TOSH PCLATH Bit 3 SP4 SP3 SP2 SP1 SP0 Holding Register for PC<20:16> Progra
PIC18F97J60 FAMILY TABLE 6-5: File Name STATUS REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — N OV Z DC C TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS T0SE PSA OSCCON IDLEN — — — ECON1 TXRST RXRST DMAST CSUMEN — — — — — IPEN — CM RI TO WDTCON RCON Values on Details on POR, BOR Page: ---x xxxx 70, 97 0000 0000 70, 171 xxxx xxxx 70, 171 1111 1111 70, 1
PIC18F97J60 FAMILY TABLE 6-5: File Name T3CON PSPCON(5) SPBRG1 REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 RD16 T3CCP2 IBF OBF Values on Details on POR, BOR Page: Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 IBOV PSPMODE — — — — 0000 ---- 71, 169 0000 0000 71, 320 EUSART1 Baud Rate Generator Register Low Byte 71, 183 RCREG1 EUSART1 Receive Register 0000 0000 71, 327 TXREG1 EUSART1 Transmit Register xxx
PIC18F97J60 FAMILY TABLE 6-5: File Name REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Values on Details on POR, BOR Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0(5) 0000 0000 72, 161 PORTE RE7(6) RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 72, 159 PORTD RD7(5) RD6(5) RD5(5) RD4(5) RD3(5) RD2 RD1 RD0 xxxx xxxx 72, 156 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 72, 153 PORTB RB7 RB6 RB5 RB4 RB3 RB
PIC18F97J60 FAMILY TABLE 6-5: File Name REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 ESTAT — BUFER — EIE — PKTIE DMAIE EDMACSH DMA Checksum Register High Byte EDMACSL DMA Checksum Register Low Byte EDMADSTH EDMADSTL EDMANDH EDMANDL EDMASTH EDMASTL ERXWRPTH ERXWRPTL ERXRDPTH ERXRDPTL ERXNDH ERXNDL ERXSTH ERXSTL ETXNDH ETXNDL ETXSTH ETXSTL EWRPTH — — — — — — Bit 1 Bit 0 r — RXBUSY TXABRT PHYRDY -0-0 -000 LINKIE TXIE — TXERIE RXERIE -000 0-00 73,
PIC18F97J60 FAMILY TABLE 6-5: File Name REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Details on POR, BOR Page: EHT7 Hash Table Register Byte 7 0000 0000 74, 259 EHT6 Hash Table Register Byte 6 0000 0000 74, 259 EHT5 Hash Table Register Byte 5 0000 0000 74, 259 EHT4 Hash Table Register Byte 4 0000 0000 74, 259 EHT3 Hash Table Register Byte 3 0000 0000 74, 259 EHT2 Hash Table Register Byte 2 0000 0000 74, 259
PIC18F97J60 FAMILY 6.3.6 STATUS REGISTER The STATUS register, shown in Register 6-3, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F97J60 FAMILY 6.4 Note: Data Addressing Modes The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way, through the program counter, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F97J60 FAMILY 6.4.3.1 FSR Registers and the INDF Operand SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
PIC18F97J60 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F97J60 FAMILY 6.6.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under the proper conditions, instructions that use the Access Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of Indexed Addressing using an offset specified in the instruction.
PIC18F97J60 FAMILY FIGURE 6-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff When a = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode.
PIC18F97J60 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F97J60 FAMILY NOTES: DS39762F-page 104 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
PIC18F97J60 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 7.2 The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”.
PIC18F97J60 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — — FREE WRERR WREN WR — bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by com
PIC18F97J60 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F97J60 FAMILY 7.3 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: The internal program memory is typically organized by words.
PIC18F97J60 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 11 bits of the TBLPTR<20:10> point to the block being erased. TBLPTR<9:0> are ignored.
PIC18F97J60 FAMILY 7.5 An on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over most of the voltage range of the device. See Parameter D132B (VPEW) for specific limits. Writing to Flash Program Memory The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory.
PIC18F97J60 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the memory block BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Row Erase operation ; disable interrupts MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64'
PIC18F97J60 FAMILY 7.5.2 WRITE VERIFY 7.5.4 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.
PIC18F97J60 FAMILY NOTES: DS39762F-page 114 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 8.0 EXTERNAL MEMORY BUS Note: The external memory bus is not implemented on 64-pin and 80-pin devices. The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8 and 16-Bit Data Width modes, and three address widths of up to 20 bits. TABLE 8-1: Name The bus is implemented with 28 pins, multiplexed across four I/O ports.
PIC18F97J60 FAMILY 8.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 8-1). This register is available in all program memory operating modes, except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions.
PIC18F97J60 FAMILY 8.2 8.2.1 Address and Data Width The PIC18F97J60 family of devices can be independently configured for different address and data widths on the same memory bus. Both address and data widths are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. The BW bit selects an 8-bit or 16-bit data bus width.
PIC18F97J60 FAMILY 8.3 Wait States While it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. In fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. To compensate for this, the external memory bus can be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting the WAIT Configuration bit.
PIC18F97J60 FAMILY 8.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD<15:0> bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. Figure 8-1 shows an example of 16-Bit Byte Write mode for PIC18F97J60 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices.
PIC18F97J60 FAMILY 8.6.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F97J60 family devices. This mode is used for word-wide memories, which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
PIC18F97J60 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Figure 8-3 shows an example of 16-Bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
PIC18F97J60 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 and Figure 8-5.
PIC18F97J60 FAMILY 8.7 will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0, must be connected to the memory devices in this mode. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing. It is inactive (asserted high) whenever the device is in Sleep mode.
PIC18F97J60 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-7 and Figure 8-8.
PIC18F97J60 FAMILY 8.8 Operation in Power-Managed Modes In alternate power-managed Run modes, the external bus continues to operate normally. If a clock source with a lower speed is selected, bus operations will run at that speed. In these cases, excessive access times for the external memory may result if Wait states have been enabled and added to external memory operations.
PIC18F97J60 FAMILY NOTES: DS39762F-page 126 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 9-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
PIC18F97J60 FAMILY Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F97J60 FAMILY 10.0 INTERRUPTS Members of the PIC18F97J60 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F97J60 FAMILY FIGURE 10-1: PIC18F97J60 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5,3,1:0> PIE2<7:5,3,1:0> IPR2<7:5,3,1:0> Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN IPEN PEIE/GIEL PIR3<7:0> PIE3<7:0> IPR3<7:0> IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2
PIC18F97J60 FAMILY 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F97J60 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External In
PIC18F97J60 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low
PIC18F97J60 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 10-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F97J60 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTRC (must be clea
PIC18F97J60 FAMILY REGISTER 10-6: R/W-0 SSP2IF (1) PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 BCL2IF(1) RC2IF(2) TX2IF(2) TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: MSSP2 Interrupt Flag bit(1) 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiti
PIC18F97J60 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F97J60 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIE CMIE ETHIE r BCL1IE — TMR3IE CCP2IE bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5
PIC18F97J60 FAMILY REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE(1) BCL2IE(1) RC2IE(2) TX2IE(2) TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IE: MSSP2 Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)(1) 1 = Enabled 0
PIC18F97J60 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F97J60 FAMILY REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 OSCFIP CMIP ETHIP r BCL1IP — TMR3IP CCP2IP bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priorit
PIC18F97J60 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP(1) BCL2IP(1) RC2IP(2) TX2IP(2) TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IP: MSSP2 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 modul
PIC18F97J60 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F97J60 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0/FLT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F97J60 FAMILY 11.0 I/O PORTS 11.1 I/O Port Pin Capabilities Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. When developing an application, the capabilities of the port pins must be considered.
PIC18F97J60 FAMILY 11.1.2 INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins are always to be avoided. Table 11-2 summarizes the input capabilities.
PIC18F97J60 FAMILY TABLE 11-3: PORTA FUNCTIONS Pin Name Function RA0/LEDA/AN0 RA0 RA1/LEDB/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4 TRIS Setting I/O 0 O DIG LATA<0> data output; not affected by analog input. I TTL PORTA<0> data input; disabled when analog input is enabled. LEDA 0 O DIG Ethernet LEDA output; takes priority over digital data. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output.
PIC18F97J60 FAMILY 11.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port; it is fully implemented on all devices. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F97J60 FAMILY TABLE 11-5: PORTB FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RB0/INT0/FLT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. 1 I ST External Interrupt 0 input. INT0 RB1/INT1 RB2/INT2 RB3/INT3/ ECCP2/P2A RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: 2: Description FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. RB1 0 O DIG LATB<1> data output.
PIC18F97J60 FAMILY TABLE 11-6: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 72 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 72 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 71 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 69 INT2IF INT1IF 69 INTCON GIE/GIEH PEIE/GIEL INTCON2
PIC18F97J60 FAMILY 11.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port; it is fully implemented on all devices. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F97J60 FAMILY TABLE 11-7: Pin Name RC0/T1OSO/ T13CKI RC1/T1OSI/ ECCP2/P2A PORTC FUNCTIONS Function TRIS Setting I/O I/O Type RC0 0 O DIG 1 I ST T1OSO x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O. ECCP2(1) 0 O DIG ECCP2 compare output and PWM output; takes priority over port data. 1 I ST ECCP2 capture input.
PIC18F97J60 FAMILY TABLE 11-8: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 72 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 72 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 11.5 PORTD, TRISD and LATD Registers PORTD is implemented as a bidirectional port in two ways: • 64-pin and 80-pin devices: 3 bits (RD<2:0>) • 100-pin devices: 8 bits (RD<7:0>) The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e.
PIC18F97J60 FAMILY TABLE 11-9: PORTD FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RD0/AD0/PSP0 (RD0/P1B) RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input; weak pull-up when RDPU bit is set. x O DIG External memory interface, Address/Data Bit 0 output.(2) x I TTL External memory interface, Data Bit 0 input.(2) x O DIG PSP read output data (LATD<0>); takes priority over port data. x I TTL PSP write data input.
PIC18F97J60 FAMILY TABLE 11-9: Pin Name RD5/AD5/ PSP5/SDI2/ SDA2(1) PORTD FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RD5(1) 0 O DIG LATD<5> data output. AD5(1) PSP5(1) RD6/AD6/ PSP6/SCK2/ SCL2(1) ST PORTD<5> data input; weak pull-up when RDPU bit is set. O DIG External memory interface, Address/Data Bit 5 output.(2) x I TTL External memory interface, Data Bit 5 input.(2) x O DIG PSP read output data (LATD<5>); takes priority over port data.
PIC18F97J60 FAMILY 11.6 PORTE, TRISE and LATE Registers PORTE is implemented as a bidirectional port in two different ways: • 64-pin devices: 6 bits wide (RE<5:0>) • 80-pin and 100-pin devices: 8 bits wide (RE<7:0>) The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e.
PIC18F97J60 FAMILY TABLE 11-11: Pin Name PORTE FUNCTIONS Function TRIS Setting I/O I/O Type RE0 0 O DIG LATE<0> data output. RE0/AD8/RD/ P2D AD8(1) RE1/AD9/WR/ P2C ST PORTE<0> data input; weak pull-up when REPU bit is set. O DIG External memory interface, Address/Data Bit 8 output.(2) x I TTL External memory interface, Data bit 8 input.(2) 1 I TTL Parallel Slave Port read enable control input.
PIC18F97J60 FAMILY TABLE 11-11: Pin Name RE5/AD13/ P1C PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE5 0 O DIG LATE<5> data output. 1 I ST PORTE<5> data input; weak pull-up when REPU bit is set. x O DIG External memory interface, Address/Data Bit 13 output.(2) x I TTL External memory interface, Data Bit 13 input.(2) P1C(3) 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data.
PIC18F97J60 FAMILY 11.7 PORTF, LATF and TRISF Registers PORTF is implemented as a bidirectional port in two different ways: Note 1: On device Resets, pins, RF<6:1>, are configured as analog inputs and are read as ‘0’. 2: To configure PORTF as digital I/O, turn off the comparators and set the ADCON1 value. • 64-pin and 80-pin devices: 7 bits wide (RF<7:1>) • 100-pin devices: 8 bits wide (RF<7:0>) The corresponding Data Direction register is TRISF.
PIC18F97J60 FAMILY TABLE 11-13: PORTF FUNCTIONS Pin Name Function RF0/AN5(1) RF1/AN6/ C2OUT RF2/AN7/ C1OUT RF3/AN8 RF4/AN9 RF5/AN10/ CVREF RF6/AN11 RF7/SS1 TRIS Setting I/O I/O Type 0 O DIG LATF<0> data output; not affected by analog input. 1 I ST PORTF<0> data input; disabled when analog input is enabled. RF0(1) AN5(1) 1 I ANA A/D Input Channel 5. Default configuration on POR. RF1 0 O DIG LATF<1> data output; not affected by analog input.
PIC18F97J60 FAMILY 11.8 PORTG, TRISG and LATG Registers Depending on the particular device, PORTG is implemented as a bidirectional port in one of three ways: • 64-pin devices: 1 bit wide (RG<4>) • 80-pin devices: 5 bits wide (RG<4:0>) • 100-pin devices: 8 bits wide (RG<7:0>) The corresponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
PIC18F97J60 FAMILY TABLE 11-15: PORTG FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RG0/ECCP3/ P3A(1) RG0(1) 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. 0 O DIG ECCP3 compare and PWM output; takes priority over port data. ECCP3(1) RG1/TX2/ CK2(1) RG2/RX2/ DT2(1) 1 I ST ECCP3 capture input. P3A(1) 0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events.
PIC18F97J60 FAMILY 11.9 Note: PORTH, LATH and TRISH Registers PORTH is available only on 80-pin and 100-pin devices. PORTH is an 8-bit wide, bidirectional I/O port; it is fully implemented on 80-pin and 100-pin devices. The corresponding Data Direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e.
PIC18F97J60 FAMILY TABLE 11-17: PORTH FUNCTIONS Pin Name RH0/A16 RH1/A17 RH2/A18 RH3/A19 RH4/AN12/P3C Function TRIS Setting I/O I/O Type RH0 0 O DIG 1 I ST PORTH<0> data input. A16(1) x O DIG External memory interface, Address Line 16. Takes priority over port data. RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. x O DIG External memory interface, Address Line 17. Takes priority over port data. RH2 0 O DIG LATH<2> data output.
PIC18F97J60 FAMILY 11.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin and 100-pin devices. PORTJ is implemented as a bidirectional port in two different ways: • 80-pin devices: 2 bits wide (RJ<5:4>) • 100-pin devices: 8 bits wide (RJ<7:0>) The corresponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
PIC18F97J60 FAMILY TABLE 11-19: PORTJ FUNCTIONS Pin Name RJ0/ALE(1) RJ1/OE(1) RJ2/WRL(1) RJ3/WRH(1) RJ4/BA0 RJ5/CE RJ6/LB(1) RJ7/UB(1) Function TRIS Setting I/O I/O Type RJ0(1) 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input; weak pull-up when RJPU bit is set. ALE(1) x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1(1) 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input; weak pull-up when RJPU bit is set.
PIC18F97J60 FAMILY 11.11 Parallel Slave Port (PSP) Note: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is only implemented on 100-pin devices. PORTD can also function as an 8-bit wide, Parallel Slave Port, or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. It is asynchronously readable and writable by the external world through the RD control input pin, RE0/AD8/RD/P2D and WR control input pin, RE1/AD9//WR/P2C.
PIC18F97J60 FAMILY REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status b
PIC18F97J60 FAMILY FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 72 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 72 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71 PORTE RE7 RE6 RE5 RE4
PIC18F97J60 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated, 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt on overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection.
PIC18F97J60 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
PIC18F97J60 FAMILY 12.3 12.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256, in power-of-2 increments, are selectable.
PIC18F97J60 FAMILY NOTES: DS39762F-page 174 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 13.
PIC18F97J60 FAMILY 13.1 cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F97J60 FAMILY 13.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F97J60 FAMILY If a high-speed circuit must be located near the oscillator (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 13-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. FIGURE 13-4: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD VSS OSC1 OSC2 RC0 RC1 RC2 Note: Not drawn to scale. 13.
PIC18F97J60 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h ; TMR1H ; TMR1L b’00001111’ ; T1CON ; secs ; mins ; .
PIC18F97J60 FAMILY 14.0 TIMER2 MODULE 14.
PIC18F97J60 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F97J60 FAMILY NOTES: DS39762F-page 182 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 15.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt on overflow • Module Reset on CCPx/ECCPx Special Event Trigger REGISTER 15-1: A simplified block diagram of the Timer3 module is shown in Figure 15-1.
PIC18F97J60 FAMILY 15.1 The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled.
PIC18F97J60 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
PIC18F97J60 FAMILY NOTES: DS39762F-page 186 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 16.0 TIMER4 MODULE 16.1 The Timer4 module has the following features: • • • • • • 8-Bit Timer register (TMR4) 8-Bit Period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register, shown in Register 16-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption.
PIC18F97J60 FAMILY 16.2 Timer4 Interrupt 16.3 The Timer4 module has an 8-Bit Period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the CCPx/ECCPx modules. It is not used as a baud rate clock for the MSSPx modules as is the Timer2 output.
PIC18F97J60 FAMILY 17.0 register. For the sake of clarity, all CCPx module operation in the following sections is described with respect to CCP4, but is equally applicable to CCP5. CAPTURE/COMPARE/PWM (CCP) MODULES Members of the PIC18F97J60 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section.
PIC18F97J60 FAMILY 17.1 CCPx Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 17.1.1 17.1.2 CCPx/ECCPx MODULES AND TIMER RESOURCES The CCPx/ECCPx modules utilize Timers 1, 2, 3 or 4, depending on the mode selected.
PIC18F97J60 FAMILY 17.2 17.2.3 Capture Mode When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin.
PIC18F97J60 FAMILY 17.3 Compare Mode Note: In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin: • • • • Can be driven high Can be driven low Can be toggled (high-to-low or low-to-high) Remains unchanged (that is, reflects the state of the I/O latch) 17.3.2 CCPx PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit.
PIC18F97J60 FAMILY TABLE 17-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN — CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 OS
PIC18F97J60 FAMILY 17.4 17.4.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. Clearing the CCP4CON or CCP5CON register will force the RG3 or RG4 output latch (depending on device configuration) to the default low level. This is not the PORTG I/O data latch.
PIC18F97J60 FAMILY The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2 (TMR4), concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by Equation 17-3: 17.4.
PIC18F97J60 FAMILY TABLE 17-4: Name INTCON REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 IPEN — CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 RCON PIR3 SSP2IF BCL2IF
PIC18F97J60 FAMILY 18.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULES In the PIC18F97J60 family of devices, three of the CCP modules are implemented as standard CCP modules with Enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The Enhanced features are discussed in detail in Section 18.4 “Enhanced PWM Mode”.
PIC18F97J60 FAMILY REGISTER 18-1: CCPxCON: ENHANCED CCPx CONTROL REGISTER (ECCP1/ECCP2/ECCP3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input/
PIC18F97J60 FAMILY 18.1 ECCPx Outputs and Configuration Each of the Enhanced CCPx modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCPx pin assignments are constant, while others change based on device configuration.
PIC18F97J60 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON Configuration ECCP Mode RC2 RD0 or RE6(1) RE5 RG4 RH7(2) RH6(2) 64-Pin Devices; 80-Pin Devices, ECCPMX = 1; 100-Pin Devices, ECCPMX = 1, Microcontroller mode or Extended Microcontroller mode with 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RD0/RE6 RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM x1xx 11xx P1A P1B P1C P1D RH7/AN15 RH6/AN14 80-Pin Devic
PIC18F97J60 FAMILY TABLE 18-3: ECCP Mode PIN CONFIGURATIONS FOR ECCP3 CCP3CON Configuration RD1 or RG0(1) RE4 RE3 RD2 or RG3(1) RH5(2) RH4(2) 64-Pin Devices; 80-Pin Devices, ECCPMX = 1; 100-Pin Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RD2/RG3 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3 RD2/RG3 RH5/AN13 RH4/AN12 Quad PWM x1xx 11xx P3A P3B P3C P3D RH5/AN13 RH4/AN12 80-Pin Devices, ECCPMX = 0; 100-Pin Devices, ECCPMX = 0, All Program
PIC18F97J60 FAMILY 18.2 Capture and Compare Modes Except for the operation of the Special Event Trigger discussed below, the Capture and Compare modes of the ECCPx modules are identical in operation to that of CCP4. These are discussed in detail in Section 17.2 “Capture Mode” and Section 17.3 “Compare Mode”. 18.2.1 Special Event Triggers are not implemented for ECCP3, CCP4 or CCP5.
PIC18F97J60 FAMILY 18.4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCPx modules and offers up to four outputs, designated PxA through PxD. Users are also able to select the polarity of the signal (either active-high or active-low).
PIC18F97J60 FAMILY 18.4.2 PWM DUTY CYCLE Note: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> bits contain the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the equation: 18.4.
PIC18F97J60 FAMILY FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 CCP1CON<7:6> SIGNAL PR2 + 1 Duty Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>
PIC18F97J60 FAMILY FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON<7:6> SIGNAL Duty Cycle 0 PR2 + 1 Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) P1B Modulated Delay(1) Delay(1) P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:
PIC18F97J60 FAMILY 18.4.4 HALF-BRIDGE MODE FIGURE 18-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge applications, as shown in Figure 18-5, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC18F97J60 FAMILY 18.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin, P1A, is continuously active and pin, P1D, is modulated. In the Reverse mode, pin, P1C, is continuously active and pin, P1B, is modulated. These are illustrated in Figure 18-6. FIGURE 18-6: P1A, P1B, P1C and P1D outputs are multiplexed with the data latches of the port pins listed in Table 18-1 and Table 18-3.
PIC18F97J60 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F97J60 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 18.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F97J60 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
PIC18F97J60 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18F97J60 FAMILY REGISTER 18-3: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCP1ASE: ECCP1 Auto-Shutdown Event Status bit 0 = ECCP1 outputs are operating 1 = A shutdown event has occurred
PIC18F97J60 FAMILY 18.4.7.1 Auto-Shutdown and Automatic Restart 18.4.8 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the P1RSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with P1RSEN = 1 (Figure 18-10), the ECCP1ASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared.
PIC18F97J60 FAMILY 18.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. 2. 3. 4. 5. 6. 7. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 (PR4) register.
PIC18F97J60 FAMILY TABLE 18-5: Name INTCON REGISTERS ASSOCIATED WITH ECCPx MODULES AND TIMER1 TO TIMER4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN — CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 O
PIC18F97J60 FAMILY NOTES: DS39762F-page 216 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 19.0 ETHERNET MODULE All members of the PIC18F97J60 family of devices feature an embedded Ethernet controller module. This is a complete connectivity solution, including full implementations of both Media Access Control (MAC) and Physical Layer (PHY) transceiver modules. Two pulse transformers and a few passive components are all that are required to connect the microcontroller directly to an Ethernet network. The Ethernet module meets all of the IEEE 802.
PIC18F97J60 FAMILY 19.1 19.1.1 Physical Interfaces and External Connections SIGNAL AND POWER INTERFACES PIC18F97J60 family devices all provide a dedicated 4-pin signal interface for the Ethernet module. No other microcontroller or peripheral functions are multiplexed with these pins, so potential device configuration conflicts do not need to be considered.
PIC18F97J60 FAMILY MAGNETICS, TERMINATION AND OTHER EXTERNAL COMPONENTS To complete the Ethernet interface, the Ethernet module requires several standard components to be installed externally. These components should be connected, as shown in Figure 19-2. The internal analog circuitry in the PHY module requires that an external resistor (2.26 k) be attached from RBIAS to ground. The resistor influences the TPOUT+/signal amplitude.
PIC18F97J60 FAMILY 19.1.5 EMI EMISSIONS CONSIDERATIONS Most locales have limits on unintentional EMI or EMC emissions that govern the amount of electromagnetic energy that may be radiated into the environment across a range of test frequencies. Ethernet applications normally do not include intentional radio frequency emissions sources. They may experience occasional regulatory failures though, due to the relative ease at which high-frequency noise may radiate out of a long attached Ethernet cable.
PIC18F97J60 FAMILY When the select line is raised high, the A ports of the switches will connect with the B1 ports, leaving the B0 ports disconnected. This will swap the RX polarity and route the TPIN+ pin to the signal on RJ-45 Jack Pin 6. TPIN- will connect to RJ-45 Pin 3. This swapped polarity can correct an incorrectly wired signal generated at the remote link partner or in the intermediate cabling. immediate response.
PIC18F97J60 FAMILY 19.2 Ethernet Buffer and Register Spaces The Ethernet module uses three independent memory spaces for its operations: • An Ethernet RAM buffer which stores packet data as it is received and being prepared for transmission. • A set of 8-bit Special Function Registers (SFRs), used to control the module, and pass data back and forth between the module and microcontroller core. • A separate set of 16-bit PHY registers used specifically for PHY control and status reporting.
PIC18F97J60 FAMILY 19.2.1 ETHERNET BUFFER AND BUFFER POINTER REGISTERS The Ethernet buffer contains the transmit and receive memory used by the Ethernet controller. The entire buffer is 8 Kbytes, divided into separate receive and transmit buffer spaces. The sizes and locations of transmit and receive memory are fully definable using the pointers in the Ethernet SFR space. The organization of the memory space and the relationships of the pointers are shown in Figure 19-5.
PIC18F97J60 FAMILY FIGURE 19-5: ETHERNET BUFFER ORGANIZATION Transmit Buffer Start (ETXSTH:ETXSTL) Buffer Write Pointer (EWRPTH:EWRPTL) Transmit Buffer End (ETXNDH:ETXNDL) Receive Buffer Start (ERXSTH:ERXSTL) 0000h Write Buffer Data (data AAh moved to EDATA) AAh Transmit Buffer Receive Buffer (Circular FIFO) Buffer Read Pointer (ERDPTH:ERDPTL) Receive Buffer End (ERXNDH:ERXNDL) DS39762F-page 224 Read Buffer Data (data 55h moved out of EDATA) 55h 1FFFh 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 19.2.1.2 Receive Buffer The receive buffer constitutes a circular FIFO buffer managed by hardware. The register pairs, ERXSTH:ERXSTL and ERXNDH:ERXNDL, serve as pointers to define the buffer’s size and location within the memory. The byte pointed to by the ERXST pair and the byte pointed to by the ERXND pair are both included in the FIFO buffer. As bytes of data are received from the Ethernet interface, they are written into the receive buffer sequentially.
PIC18F97J60 FAMILY 19.2.1.3 Transmit Buffer Any space within the 8-Kbyte memory which is not programmed as part of the receive FIFO buffer is considered to be the transmit buffer. The responsibility of managing where packets are located in the transmit buffer belongs to the application. Whenever the application decides to transmit a packet, the ETXST and ETXND Pointers are programmed with addresses specifying where, within the transmit buffer, the particular packet to transmit is located.
PIC18F97J60 FAMILY 19.2.2 SFRs AND THE ETHERNET MODULE Like other peripherals, direct control of the Ethernet module is accomplished through a set of SFRs. Because of their large number, the majority of these registers is located in the bottom half of Bank 14 of the microcontroller’s data memory space. Five key SFRs for the Ethernet module are located in the microcontroller’s regular SFR area in Bank 15, where fast access is possible.
PIC18F97J60 FAMILY REGISTER 19-2: ECON2: ETHERNET CONTROL REGISTER 2 R/W-1 R/W-0(1) R/W-0 U-0 U-0 U-0 U-0 U-0 AUTOINC PKTDEC ETHEN — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 AUTOINC: Automatic Buffer Pointer Increment Enable bit 1 = Automatically increment ERDPT or EWRPT registers on reading from, or writing to, EDATA 0 = Do not automatically ch
PIC18F97J60 FAMILY 19.2.4 MAC AND MII REGISTERS Note 1: Do not access the MAC and MII SFRs unless the Ethernet module is enabled (ETHEN = 1). These SFRs are used to control the operations of the MAC, and through the MIIM, the PHY. The MAC and MII registers occupy data addresses, E80h-E85h, E8Ah and EA0h through EB9h. Although MAC and MII registers appear in the general memory map of the microcontroller, these registers are embedded inside the MAC module.
PIC18F97J60 FAMILY REGISTER 19-5: MACON3: MAC CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 PADCFG<2:0>: Automatic Pad and CRC Configuration bits 111 = All short frames are zero-padded to 64 bytes and a valid CRC will then be appe
PIC18F97J60 FAMILY REGISTER 19-6: MACON4: MAC CONTROL REGISTER 4 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0 — DEFER r r — — r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 DEFER: Defer Transmission Enable bit (applies to half duplex only) 1 = When the medium is occupied, the MAC waits indefinitely for it to
PIC18F97J60 FAMILY REGISTER 19-8: MISTAT: MII STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — r NVALID SCAN BUSY bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 Reserved: Do not use bit 2 NVALID: MII Management Read Data Not Valid bit 1 = The contents of the MIRD registers are not valid yet 0 =
PIC18F97J60 FAMILY To read from a PHY register: 1. 2. 3. 4. 5. Write the address of the PHY register to be read into the MIREGADR register. Set the MIIRD bit (MICMD<0>). The read operation begins and the BUSY bit (MISTAT<0>) is set after two TCY. Wait 10.24 s, then poll the BUSY bit to be certain that the operation is complete. When the MAC has obtained the register contents, the BUSY bit will clear itself.
Addr PIC18F97J60 FAMILY PHY REGISTER SUMMARY Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values 00h PHCON1 r r — — r r — PDPXMD r — — — — — — — 00-- 00-0 0--- ---- 01h PHSTAT1 — — — r r — — — — — — — — LLSTAT r — ---1 1--- ---- -00- 10h PHCON2 — FRCLNK r r r r r HDLDIS r r r RXAPDIS r r r r -000 0000 0000 0000 11h PHSTAT2 — — LSTAT r — — — r — — — —
PIC18F97J60 FAMILY REGISTER 19-9: PHCON1: PHY CONTROL REGISTER 1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 r r — — r r — PDPXMD bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 r — — — — — — — bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Reserved: Write as ‘0’ bit 13-12 Unimplemented: Read as ‘0’ bit 11-10 Reserved
PIC18F97J60 FAMILY REGISTER 19-11: PHCON2: PHY CONTROL REGISTER 2 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FRCLNK r r r r r HDLDIS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r RXAPDIS r r r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 FRCLNK: PHY Force Lin
PIC18F97J60 FAMILY REGISTER 19-12: PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2 U-0 U-0 R-0 R-0 R-0 R-0 R-x U-0 — — TXSTAT RXSTAT COLSTAT LSTAT r — bit 15 bit 8 U-0 U-0 R-0 U-0 U-0 U-0 U-0 U-0 — — r — — — — — bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXSTAT: PHY Transmit Status bit 1
PIC18F97J60 FAMILY REGISTER 19-13: PHLCON: PHY MODULE LED CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 r r r r LACFG3 LACFG2 LACFG1 LACFG0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-x LBCFG3 LBCFG2 LBCFG1 LBCFG0 LFRQ1 LFRQ0 STRCH r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 x = Bit is unknown Reserve
PIC18F97J60 FAMILY 19.3 Ethernet Interrupts Note: The Ethernet module can generate multiple interrupt conditions. To accommodate all of these sources, the module has its own interrupt logic structure, similar to that of the microcontroller. Separate sets of registers are used to enable and flag different interrupt conditions. The EIE register contains the individual interrupt enable bits for each source, while the EIR register contains the corresponding interrupt flag bits.
PIC18F97J60 FAMILY REGISTER 19-14: EIE: ETHERNET INTERRUPT ENABLE REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 PKTIE: Receive Packet Pending Interrupt Enable bit 1 = Enable receive packet pending interrupt 0 = Disable receive packet pending interrupt
PIC18F97J60 FAMILY REGISTER 19-15: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER U-0 R-0 R/C-0 R-0 R/C-0 U-0 R/C-0 R/C-0 — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PKTIF: Receive Packet Pending Interrupt Flag bit 1 = Receive buffer contains one or more unprocessed packets; clear
PIC18F97J60 FAMILY REGISTER 19-16: PHIE: PHY INTERRUPT ENABLE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 r r r r r r r r bit 15 bit 8 R-0 R-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 r r r PLNKIE r r PGEIE r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Reserved: Write as ‘0’, ignore on read bit 5 Reserved: Maintain as ‘0’ bit 4 PLNKIE: PHY Link C
PIC18F97J60 FAMILY 19.3.1.1 Receive Error Interrupt (RXERIF) 4. The receive error interrupt is used to indicate that a packet being received was aborted due to an error condition. Three errors are possible: 1. 2. 3.
PIC18F97J60 FAMILY 19.3.1.4 Link Change Interrupt (LINKIF) The LINKIF indicates that the link status has changed. The actual current link status can be obtained from the LLSTAT (PHSTAT1<2>) or LSTAT (PHSTAT2<10>) bits (see Register 19-10 and Register 19-12). Unlike other interrupt sources, the link status change interrupt is created in the integrated PHY module; additional steps must be taken to enable it. By Reset default, LINKIF is never set for any reason.
PIC18F97J60 FAMILY 19.4 Module Initialization Before the Ethernet module can be used to transmit and receive packets, certain device settings must be initialized. Depending on the application, some configuration options may need to be changed. Normally, these tasks may be accomplished once after Reset and do not need to be changed thereafter. Before any other configuration actions are taken, it is recommended that the module be enabled by setting the ETHEN bit (ECON2<5>).
PIC18F97J60 FAMILY REGISTER 19-18: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-0 BBIPG<6:0>: Back-to-Back Inter-Packet Gap Delay Time bits When FULDPX (MACON3<0>) = 1: Nibble t
PIC18F97J60 FAMILY 19.5 Transmitting and Receiving Data The Ethernet protocol (IEEE Standard 802.3) provides an extremely detailed description of the 10 Mbps, frame-based serial communications system. Before discussing the actual use of the Ethernet module, a brief review of the structure of a typical Ethernet data frame may be appropriate. It is assumed that users already have some familiarity with IEEE 802.3.
PIC18F97J60 FAMILY 19.5.1.2 Destination Address The destination address field is a 6-byte field filled with the MAC address of the device that the packet is directed to. If the Least Significant bit in the first byte of the MAC address is set, the address is a Multicast destination. For example, 01-00-00-00-F0-00 and 33-45-67-89-AB-CD are Multicast addresses, while 00-00-00-00-F0-00 and 32-45-67-89-AB-CD are not.
PIC18F97J60 FAMILY 19.5.2 TRANSMITTING PACKETS The Ethernet module’s MAC will automatically generate the preamble and Start-of-Frame (SOF) delimiter fields when transmitting. Additionally, the MAC can generate any padding (if needed) and the CRC if configured to do so. The application must generate and write all other frame fields into the buffer memory for transmission. FIGURE 19-9: — In addition, the Ethernet module requires a single per-packet control byte to precede the packet for transmission.
PIC18F97J60 FAMILY An example of how the entire assembled transmit packet looks in memory is shown in Figure 19-10. To construct and transmit a packet in this fashion: 1. 2. 3. 4. 5. Set the ETXST Pointers to an appropriate unused location in the buffer. This will be the location of the per-packet control byte. In the example, it would be 0120h. It is recommended that an even address be used for the ETXST Pointers.
PIC18F97J60 FAMILY TABLE 19-4: Bit 55-52 TRANSMIT STATUS VECTORS Field Description Zero 0 51 Transmit VLAN Tagged Frame Frame’s length/type field contained 8100h which is the VLAN protocol identifier. 50 Backpressure Applied Reserved, do not use. 49 Transmit Pause Control Frame The frame transmitted was a control frame with a valid pause opcode. 48 Transmit Control Frame The frame transmitted was a control frame.
PIC18F97J60 FAMILY 19.5.3 RECEIVING PACKETS Assuming that the receive buffer has been initialized, the MAC has been properly configured and the receive filters have been configured, the application should perform these steps to receive Ethernet packets: 1. 2. 3. Set the PKTIE and ETHIE bits to generate an Ethernet interrupt whenever a packet is received (if desired).
PIC18F97J60 FAMILY TABLE 19-5: RECEIVE STATUS VECTORS Bit Field Description 31 Zero ‘0’ 30 Receive VLAN Type Detected Current frame was recognized as a VLAN tagged frame. 29 Receive Unknown Opcode Current frame was recognized as a control frame, but it contained an unknown opcode. 28 Receive Pause Control Frame Current frame was recognized as a control frame containing a valid pause frame opcode and a valid destination address.
PIC18F97J60 FAMILY 19.5.3.3 Freeing Receive Buffer Space After the user application has processed a packet (or part of the packet) and needs to free the occupied buffer space used by the processed data, it must advance the Receive Buffer Read Pointer pair, ERXRDPT. The module always writes up to, but not over, the memory pointed to by the ERXRDPT registers.
PIC18F97J60 FAMILY TABLE 19-6: Register Name SUMMARY OF REGISTERS ASSOCIATED WITH PACKET TRANSMISSION Reset Values on Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EIE — PKTIE DMAIE LINKIE TXIE — TXERIE RXERIE 73 EIR — PKTIF DMAIF LINKIF TXIF — TXERIF RXERIF 73 ESTAT — BUFER — r — RXBUSY TXABRT PHYRDY 73 TXRST RXRST DMAST CSUMEN TXRTS RXEN — — 70 ECON1 ETXSTL Transmit Start Register Low Byte (ETXST<7:0>) — ETXSTH ETXNDL — — 74 Transmit Start Reg
PIC18F97J60 FAMILY 19.6 Duplex Mode Configuration and Negotiation The Ethernet module does not support Automatic Duplex mode negotiation. If it is connected to an automatic duplex negotiation-enabled network switch or Ethernet controller, the module will be detected as a half-duplex device. To communicate in full duplex, the module and the remote node (switch, router or Ethernet controller) must be manually configured for full-duplex operation. 19.6.
PIC18F97J60 FAMILY 19.7 Flow Control The Ethernet module implements hardware flow control for both Full and Half-Duplex modes. The operation of this feature differs depending on which mode is being used. 19.7.1 HALF-DUPLEX MODE In Half-Duplex mode, setting the FCEN0 bit (EFLOCON<0>) causes flow control to be enabled. When FCEN0 is set, a continuous preamble pattern of alternating ‘1’s and ‘0’s (55h) will automatically be transmitted on the Ethernet medium.
PIC18F97J60 FAMILY To enable flow control in Full-Duplex mode, set the TXPAUS and RXPAUS bits in the MACON1 register. Then, at any time that the receiver buffer is running out of space, set the Flow Control Enable bits, FCEN<1:0> (EFLOCON<1:0>). The module will automatically finish transmitting anything that was in progress and then send a valid pause frame, loaded with the selected pause timer value.
PIC18F97J60 FAMILY 19.8 Receive Filters 19.8.4 HASH TABLE FILTER To minimize microcontroller processing overhead, the Ethernet module incorporates a range of different receive filters which can automatically reject packets which are not needed. Six different types of packet filters are implemented: The Hash Table receive filter is typically used to receive traffic sent to a specific Multicast group address.
PIC18F97J60 FAMILY REGISTER 19-20: ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UCEN: Unicast Filter Enable bit When ANDOR = 1: 1 = Packets not having a destination address matching the local MAC address will be discarded
PIC18F97J60 FAMILY FIGURE 19-13: RECEIVE FILTERING USING OR LOGIC Packet Detected on Wire, ANDOR = 0 (OR) UCEN, PMEN, MPEN, HTEN, MCEN and BCEN all clear? Yes No UCEN set? Yes No PMEN set? Unicast packet? Yes No Pattern matches? No Yes No Yes CRCEN set? Yes CRCEN valid? Yes Accept Packet No No Reject Packet MPEN set? Yes No HTEN set? Yes Hash table bit set? Yes No Yes No BCEN set? Yes No No MCEN set? Magic Packet™ for us? Multicast destination? Yes No Yes No
PIC18F97J60 FAMILY FIGURE 19-14: RECEIVE FILTERING USING AND LOGIC Packet Detected on Wire, ANDOR = 1 (AND) UCEN set? Yes No Unicast packet? No Yes PMEN set? Yes No Pattern Matches? No Yes MPEN set? Yes Magic Packet™ for us? No No Yes HTEN set? Yes No Hash Table bit set? No Yes MCEN set? Yes Multicast destination? No No Yes BCEN set? Yes Broadcast destination? No No Yes No CRCEN set? Yes CRC valid? No Yes Accept Packet DS39762F-page 262 Reject Packet 2011 Micr
PIC18F97J60 FAMILY 19.8.5 PATTERN MATCH FILTER The Pattern Match Checksum registers should be programmed to the checksum which is expected for the selected bytes. The checksum is calculated in the same manner that the DMA module calculates checksums (see Section 19.9.2 “Checksum Calculations”). Data bytes which have corresponding mask bits programmed to ‘0’ are completely removed for purposes of calculating the checksum, as opposed to treating the data bytes as zero.
PIC18F97J60 FAMILY 19.8.6 MAGIC PACKET FILTER The Magic Packet pattern consists of a sync pattern of 6 FFh bytes, followed by 16 repeats of the destination address (Figure 19-16). The Magic Packet filter checks the destination address and data fields of all incoming packets. If the destination address matches the MAADR registers and the data field holds a valid Magic Packet pattern someplace within it, then the packet will meet the Magic Packet filter criteria.
PIC18F97J60 FAMILY 19.9 Direct Memory Access Controller The Ethernet module incorporates a dual purpose DMA controller, which can be used to copy data between locations within the 8-Kbyte memory buffer. It can also be used to calculate a 16-bit checksum which is compatible with various industry standard communication protocols, including TCP, UDP, IP, ICMP, etc.
PIC18F97J60 FAMILY 19.9.2 CHECKSUM CALCULATIONS When the checksum is finished being calculated, the hardware will clear the DMAST bit, set the DMAIF bit and an interrupt will be generated, if enabled. The DMA Pointers will not be modified and no memory will be written to. The EDMACSH and EDMACSL registers will contain the calculated checksum.
PIC18F97J60 FAMILY 19.10 Module Resets 19.10.2 The Ethernet module provides selective module Resets: The Transmit Only Reset is performed by writing a ‘1’ to the TXRST bit (ECON1<7>). This resets the transmit logic only. Other register and control blocks, such as buffer management and host interface, are not affected by a Transmit Only Reset event. To return to normal operation, the TXRST bit must be cleared in software.
PIC18F97J60 FAMILY NOTES: DS39762F-page 268 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 20.0 20.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F97J60 FAMILY 20.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. Each MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.
PIC18F97J60 FAMILY REGISTER 20-2: R/W-0 SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 WCOL SSPOV (1) R/W-0 (2) SSPEN R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPxBUF register is written while it is still transmitting
PIC18F97J60 FAMILY 20.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC18F97J60 FAMILY 20.3.3 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins.
PIC18F97J60 FAMILY 20.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 2, Figure 20-2) will broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC18F97J60 FAMILY 20.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit (SSPxCON1<4>). While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin.
PIC18F97J60 FAMILY FIGURE 20-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF FIGURE 20-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 7 bit
PIC18F97J60 FAMILY 20.3.8 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode. In the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTRC source. See Section 3.7 “Clock Sources and Oscillator Switching” for additional information. 20.3.
PIC18F97J60 FAMILY TABLE 20-2: Name INTCON REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 GIE/GIEH PEIE/GIEL TMR0IE Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF(1) BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71
PIC18F97J60 FAMILY 20.4 I2C Mode 20.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F97J60 FAMILY REGISTER 20-3: R/W-0 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabl
PIC18F97J60 FAMILY REGISTER 20-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were no
PIC18F97J60 FAMILY REGISTER 20-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) Unused in Master mode.
PIC18F97J60 FAMILY REGISTER 20-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the
PIC18F97J60 FAMILY 20.4.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I 2C operation.
PIC18F97J60 FAMILY 20.4.3.2 Address Masking Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to 31 addresses in 7-bit mode, and up to 63 addresses in 10-bit mode (see Example 20-2). The I2C Slave behaves the same way whether address masking is used or not.
PIC18F97J60 FAMILY 20.4.3.3 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set, or bit, SSPOV (SSPxCON1<6>), is set.
2011 Microchip Technology Inc. 2 CKP 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S SDAx A6 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full.
DS39762F-page 288 2 A6 Note CKP 3 4 X 5 A3 Receiving Address A5 6 X 1 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. 9 D7 x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
2011 Microchip Technology Inc.
DS39762F-page 290 2 1 3 1 5 0 7 A8 UA is set indicating that the SSPxADD needs to be updated 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) 6 A9 SSPxBUF is written with contents of SSPxSR Cleared in software BF (SSPxSTAT<0>) CKP 1 4 SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of addres
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DS39762F-page 292 2 1 3 1 4 1 CKP (SSPxCON1<4>) UA (SSPxSTAT<1>) BF (SSPxSTAT<0>) 5 0 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address 6 8 A6 A5 A4 A3 A2 A1 A0 Receive Second Byte of Address Dummy read
PIC18F97J60 FAMILY 20.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. 20.4.4.
PIC18F97J60 FAMILY 20.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 20-14: already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx.
2011 Microchip Technology Inc.
DS39762F-page 296 2 1 3 1 UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) CKP 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18F97J60 FAMILY 20.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices.
PIC18F97J60 FAMILY MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F97J60 FAMILY 20.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock.
PIC18F97J60 FAMILY 20.4.7 BAUD RATE 20.4.7.1 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 20-19). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F97J60 FAMILY 20.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 20-20: SDAx SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting.
PIC18F97J60 FAMILY I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low.
PIC18F97J60 FAMILY 20.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<6:0> and begins counting.
PIC18F97J60 FAMILY 20.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification Parameter 106).
2011 Microchip Technology Inc.
DS39762F-page 306 S ACKEN SSPOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1 while CPU responds to SSPxIF SSPxIF SCLx SDAx 1 A7 2 4 5 Cleared in software 3 6 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 9 R/W = 1 ACK 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 D7 D6 D5 D4 D3 D2 D1 Cleared in software Set SSPxIF at end of receive 9 ACK is not sent ACK P Set SSPxIF int
PIC18F97J60 FAMILY 20.4.12 ACKNOWLEDGE SEQUENCE TIMING 20.4.13 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18F97J60 FAMILY 20.4.14 SLEEP OPERATION 20.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 20.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 20.4.
PIC18F97J60 FAMILY 20.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 20-28). SCLx is sampled low before SDAx is asserted low (Figure 20-29). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 20-30).
PIC18F97J60 FAMILY FIGURE 20-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC18F97J60 FAMILY 20.4.17.2 Bus Collision During a Repeated Start Condition reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs.
PIC18F97J60 FAMILY 20.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 20-33).
PIC18F97J60 FAMILY TABLE 20-4: Name REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 INTCON Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP PIR2 OSCFIF CMIF ETHIF r BCL1IF — TMR3IF CCP2IF 71 PIE2 OSCFIE
PIC18F97J60 FAMILY NOTES: DS39762F-page 314 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 21.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F97J60 FAMILY REGISTER 21-1: R/W-0 CSRC TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F97J60 FAMILY REGISTER 21-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabled (held in R
PIC18F97J60 FAMILY REGISTER 21-3: BAUDCONx: BAUD RATE CONTROL REGISTER x R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No B
PIC18F97J60 FAMILY 21.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSARTx. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F97J60 FAMILY EQUATION 21-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate=16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F97J60 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRG16 = 0, BRGH = 0 BAUD RATE (K) FOSC = 41.667 MHz Actual Rate (K) % Error FOSC = 31.25 MHz SPBRG Actual Value Rate (K) (decimal) % Error FOSC = 25.000 MHz SPBRG Actual Value Rate (K) (decimal) % Error FOSC = 20.833 MHz SPBRG Actual Value Rate (K) (decimal) % Error SPBRG Value (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — — — — 1.271 5.96 255 135 2.4 2.543 5.96 255 2.405 0.
PIC18F97J60 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRG16 = 1, BRGH = 0 BAUD RATE (K) FOSC = 41.667 MHz FOSC = 31.25 MHz SPBRG Actual Value Rate (K) (decimal) FOSC = 25.000 MHz SPBRG Actual Value Rate (K) (decimal) FOSC = 20.833 MHz SPBRG Actual Value Rate (K) (decimal) % Error SPBRG Value (decimal) 0.300 0.00 4339 1.200 0.00 1084 650 2.398 -0.09 542 -0.15 162 9.574 -0.27 135 0.47 80 19.148 -0.27 67 Actual Rate (K) % Error 0.3 0.300 0.
PIC18F97J60 FAMILY 21.1.3 AUTO-BAUD RATE DETECT The Enhanced USARTx module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 21-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. While the ABD sequence takes place, the EUSARTx state machine is held in Idle.
PIC18F97J60 FAMILY FIGURE 21-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h 001Ch Start RXx pin Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSARTx module to be configured in Asynchronous mode and WUE = 0.
PIC18F97J60 FAMILY 21.2 EUSARTx Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTAx<4>). In this mode, the EUSARTx uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip, dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSARTx transmits and receives the LSb first.
PIC18F97J60 FAMILY FIGURE 21-3: EUSARTx TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8) Pin Buffer and Control 0 TSR Register TXx pin Interrupt TXEN Baud Rate CLK TRMT SPEN TXCKP BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator FIGURE 21-4: TX9D ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TXx NOT INVERTED) Write to TXREGx BRG Output (Shift Clock) Word 1 TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg.
PIC18F97J60 FAMILY TABLE 21-5: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF(1) TMR4IF CCP5IF CCP4IF
PIC18F97J60 FAMILY 21.2.2 EUSARTx ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 21-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. The RXDTP bit (BAUDCON<5>) allows the RXx signal to be inverted (polarity reversed).
PIC18F97J60 FAMILY FIGURE 21-6: EUSARTx RECEIVE BLOCK DIAGRAM CREN FERR OERR x64 Baud Rate CLK BRG16 SPBRGHx 64 or 16 or 4 SPBRGx Baud Rate Generator RSR Register MSb Stop (8) 7 LSb 1 0 Start RX9 Pin Buffer and Control Data Recovery RXx RX9D RCREGx Register FIFO RXDTP SPEN 8 Interrupt FIGURE 21-7: Data Bus RCxIF RCxIE ASYNCHRONOUS RECEPTION, RXDTP = 0 (RXx NOT INVERTED) Start bit RXx (pin) bit 0 bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0
PIC18F97J60 FAMILY 21.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSARTx are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line while the EUSARTx is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>).
PIC18F97J60 FAMILY FIGURE 21-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note 1: The EUSARTx remains in Idle while the WUE bit is set.
PIC18F97J60 FAMILY 21.2.5 BREAK CHARACTER SEQUENCE The EUSARTx module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift Register (TSR) is loaded with data.
PIC18F97J60 FAMILY 21.3 Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
PIC18F97J60 FAMILY FIGURE 21-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).
PIC18F97J60 FAMILY 21.3.2 EUSARTx SYNCHRONOUS MASTER RECEPTION 4. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>), or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F97J60 FAMILY TABLE 21-8: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF(1) TX2IF TMR4IF CCP5IF CCP4
PIC18F97J60 FAMILY 21.4 To set up a Synchronous Slave Transmission: EUSARTx Synchronous Slave Mode 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 2. 3. 21.4.1 EUSARTx SYNCHRONOUS SLAVE TRANSMISSION 4. 5. 6.
PIC18F97J60 FAMILY 21.4.2 EUSARTx SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode, and bit, SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F97J60 FAMILY 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 11 inputs for the 64-pin devices, 15 inputs for the 80-pin devices and 16 inputs for the 100-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
PIC18F97J60 FAMILY REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PCFG<3:0> AN8 AN7 AN6 AN5(2) AN4 AN3 AN2 AN1(3) AN0(3) PCFG<3:0>: A/D Port Configuration Control bits: AN9 bit 3-0 AN10 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1
PIC18F97J60 FAMILY REGISTER 22-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110
PIC18F97J60 FAMILY The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF, is set.
PIC18F97J60 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 22.1 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. 2. 3.
PIC18F97J60 FAMILY 22.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 22-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F97J60 FAMILY 22.2 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F97J60 FAMILY 22.5 A/D Conversions 22.6 Figure 22-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. An A/D conversion can be started by the “Special Event Trigger” of the ECCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set).
PIC18F97J60 FAMILY 22.7 A/D Converter Calibration The A/D Converter in the PIC18F97J60 family of devices includes a self-calibration feature which compensates for any offset generated within the module. The calibration process is automated and is initiated by setting the ADCAL bit (ADCON0<7>). The next time the GO/DONE bit is set, the module will perform a “dummy” conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for offset.
PIC18F97J60 FAMILY NOTES: DS39762F-page 348 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 23.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs, multiplexed with pins, RF1 through RF6, as well as the on-chip voltage reference (see Section 24.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.
PIC18F97J60 FAMILY 23.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 23-1. Bits CM<2:0> of the CMCON register are used to select these modes. The TRISF register controls the data direction of the comparator pins for each mode.
PIC18F97J60 FAMILY 23.2 23.3.2 Comparator Operation A single comparator is shown in Figure 23-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level.
PIC18F97J60 FAMILY + To CxOUT pin - Port Pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 23-3: D Bus Data Q CxINV Read CMCON EN D Q EN CL From Other Comparator Reset 23.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F97J60 FAMILY 23.9 range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 23-4.
PIC18F97J60 FAMILY NOTES: DS39762F-page 354 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 24.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 24-1.
PIC18F97J60 FAMILY FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR<3:0> R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 24.2 Comparator Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 24-1) keep CVREF from approaching the reference source rails.
PIC18F97J60 FAMILY FIGURE 24-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXJ6X CVREF Module Note 1: TABLE 24-1: Name CVRCON R(1) Voltage Reference Output Impedance + – RF5 CVREF Output R is dependent upon the comparator voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>.
PIC18F97J60 FAMILY NOTES: DS39762F-page 358 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 25.0 SPECIAL FEATURES OF THE CPU PIC18F97J60 family devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F97J60 FAMILY TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs File Name 300000h CONFIG1L Default/ Unprogrammed Value(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEBUG XINST STVREN — — — — WDTEN 110- ---1 (2) (2) (2) (2) (3) 300001h CONFIG1H — CP0 — — ---- 01-- 300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111 300004h CONFIG3L WAIT(4) BW(4) EMB1(4) — —
PIC18F97J60 FAMILY REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-0 U-0 U-0 U-0 U-0 R/WO-1 DEBUG XINST STVREN — — — — WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins 0 = Back
PIC18F97J60 FAMILY REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-
PIC18F97J60 FAMILY REGISTER 25-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 —(1) —(1) —(1) —(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:
PIC18F97J60 FAMILY REGISTER 25-5: R/WO-1 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 (1) BW WAIT (1) R/WO-1 R/WO-1 (1) (1) EMB1 EMB0 R/WO-1 EASHFT (1) U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states for operations on external memory bus is disabled 0 = Wait s
PIC18F97J60 FAMILY REGISTER 25-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 (1) (1) (1) (1) — — — — U-0 — R/WO-1 ETHLED R/WO-1 ECCPMX (2) R/WO-1 CCP2MX(2) bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 ETHLED: Ethernet LED Enable bit 1 = RA0/RA1 are multiplexed with LEDA/LEDB when t
PIC18F97J60 FAMILY REGISTER 25-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F97J60 FAMILY DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits See Register 25-8 for a complete listing. bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision.
PIC18F97J60 FAMILY 25.2 Watchdog Timer (WDT) For PIC18F97J60 family devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexor, controlled by the WDTPS bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.
PIC18F97J60 FAMILY REGISTER 25-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit
PIC18F97J60 FAMILY 25.3 On-Chip Voltage Regulator All of the PIC18F97J60 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC18F97J60 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin.
PIC18F97J60 FAMILY 25.4 In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available.
PIC18F97J60 FAMILY 25.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
PIC18F97J60 FAMILY FIGURE 25-5: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 25.5.3 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexor selects the clock source selected by the OSCCON register.
PIC18F97J60 FAMILY 25.6 Program Verification and Code Protection For all devices in the PIC18F97J60 family, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. 25.6.1 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against untoward changes or reads in two ways.
PIC18F97J60 FAMILY NOTES: DS39762F-page 374 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 26.0 INSTRUCTION SET SUMMARY The PIC18F97J60 family of devices incorporates the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 26.
PIC18F97J60 FAMILY TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F97J60 FAMILY FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE
PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subt
PIC18F97J60 FAMILY 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F97J60 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F97J60 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 n 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F97J60 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] f, b {,a} Operation: 0 f Status Affected: None Encoding: 1001 Description: Operands: -128 n 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F97J60 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F97J60 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F97J60 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F97J60 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F97J60 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted.
PIC18F97J60 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>; if s = 1, (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F97J60 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f, 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F97J60 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F97J60 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
PIC18F97J60 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6 W<7:4>, C =1; else (W<7:4>) W<7:4> Status Affected: 0000 Description: C Encoding: 0000 0000 0000 DAW adjusts the e
PIC18F97J60 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F97J60 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F97J60 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F97J60 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F97J60 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
PIC18F97J60 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Status Affected: None Operation: (fs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F97J60 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F97J60 FAMILY MULLW Multiply Literal with W MULWF Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte.
PIC18F97J60 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 f 255 a [0,1] f {,a} Operation: (f) + 1 f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
PIC18F97J60 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F97J60 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F97J60 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: Q2 Q3 Q4 Decode No operation No operation POP PC from
PIC18F97J60 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine.
PIC18F97J60 FAMILY RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F97J60 FAMILY RRNCF Rotate Right f (no carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) dest, (f<0>) dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F97J60 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F97J60 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F97J60 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F97J60 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD*, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change if TBLRD*+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD*-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: Status Affected
PIC18F97J60 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT*+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00A356
PIC18F97J60 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F97J60 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18F97J60 FAMILY 26.2 A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions are provided in Section 26.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 26-1 (page 376) apply to both the standard and extended PIC18 instruction sets.
PIC18F97J60 FAMILY 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: FSR(f) + k FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F97J60 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F97J60 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operands: 0k 255 Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.
PIC18F97J60 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSRf – k FSRf FSR2 – k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F97J60 FAMILY 26.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 “Indexed Addressing with Literal Offset”).
PIC18F97J60 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the valu
PIC18F97J60 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F97J60 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F97J60 FAMILY 27.
PIC18F97J60 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.
PIC18F97J60 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F97J60 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F97J60 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any digital only input pin or MCLR with respect to VSS (except VDD) ..................................
PIC18F97J60 FAMILY FIGURE 28-1: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (ENVREG TIED TO VDD) 4.0V 3.6V 3.5V Voltage (VDD)(1) PIC18F6XJ6X/8XJ6X/9XJ6X 3.0V 2.7V 2.5V 2.0V 0 Frequency 41.6667 MHz When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset before VDD reaches a level at which full-speed operation is not possible. Note 1: FIGURE 28-2: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (ENVREG TIED TO VSS) 3.
PIC18F97J60 FAMILY 28.1 DC Characteristics: Supply Voltage, PIC18F97J60 Family (Industrial) PIC18F97J60 Family (Industrial) Param No. Symbol Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Characteristic D001 VDD D001B VDDCORE External Supply for Microcontroller Core Supply Voltage Min Typ Max Units VDDCORE 2.7 3.1 — — — 3.6 3.6 3.6 V V V 2.0 — 2.7 V D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.
PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 19.0 69.0 A -40°C 21.0 69.0 A +25°C 45.0 149.0 A +85°C 26.0 104.0 A -40°C 29.0 104.0 A +25°C 60.0 184.0 A +85°C 40.0 203.0 A -40°C 44.0 203.0 A +25°C 105.0 209.
PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 12.0 34.0 A -40°C 12.0 34.0 A +25°C 74.0 108.0 A +85°C 20.0 45.0 A -40°C 20.0 45.0 A +25°C +85°C Supply Current (IDD)(2,3) All devices All devices 82.0 126.
PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 0.8 1.5 mA -40°C 0.8 1.5 mA +25°C 0.9 1.7 mA +85°C 1.1 1.8 mA -40°C 1.1 1.8 mA +25°C 1.2 2.0 mA +85°C 2.1 3.4 mA -40°C 2.0 3.4 mA +25°C 2.1 3.
PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 2.8 5.2 mA -40°C 2.5 5.2 mA +25°C 2.8 5.
PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 0.5 1.1 mA -40°C 0.5 1.1 mA +25°C 0.6 1.2 mA +85°C 0.9 1.4 mA -40°C 0.9 1.4 mA +25°C 1.0 1.5 mA +85°C 1.9 2.6 mA -40°C 1.8 2.6 mA +25°C 1.9 2.
PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 22.0 45.0 A -10°C 22.0 45.0 A +25°C 78.0 114.0 A +70°C 27.0 52.0 A -10°C 27.0 52.0 A +25°C +70°C Supply Current (IDD)(2) All devices All devices 92.0 135.
PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. D022 (IWDT) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device D027 IETH(6) 4: 5: 6: Units Conditions VDD = 2.0V, VDDCORE = 2.0V(4) 7.0 19.0 8.0 A A A +25°C +85°C -40°C 3.0 14.0 5.0 5.0 19.0 12.0 8.0 22.0 12.0 12.0 30.0 20.0 A A A A A A +25°C +85°C -40°C +25°C +85°C -40°C 12.0 24.0 13.0 20.0 36.0 21.
PIC18F97J60 FAMILY 28.3 DC Characteristics: PIC18F97J60 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions Input Low Voltage All I/O Ports: D030 with TTL Buffer D031 with Schmitt Trigger Buffer VSS 0.15VDD V VDD <2.7V VSS 0.8 V 2.7V VDD 3.6V VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.
PIC18F97J60 FAMILY 28.3 DC Characteristics: PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic Min Max Units Conditions PORTD, PORTE, PORTJ — 0.4 V IOL = 4 mA, VDD = 3.3V, -40C to +85C PORTA<5:2>, PORTF, PORTG, PORTH — 0.4 V IOL = 2 mA, VDD = 3.3V, -40C to +85C PORTA<1:0>, PORTB, PORTC — 0.4 V IOL = 8 mA, VDD = 3.
PIC18F97J60 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Program Flash Memory D130 EP Cell Endurance 100 1K — D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage Voltage for Self-Timed Erase or Write VDD VDDCORE 2.70 2.35 — — 3.6 2.
PIC18F97J60 FAMILY TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage* — ±5.0 ±25 mV D301 VICM Input Common-Mode Voltage* 0 — AVDD – 1.
PIC18F97J60 FAMILY 28.4 28.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F97J60 FAMILY 28.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 28-5 apply to all timing specifications unless otherwise noted. Figure 28-3 specifies the load conditions for the timing specifications. TABLE 28-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 28-3: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Operating voltage VDD range as described in DC spec Section 28.
PIC18F97J60 FAMILY 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 28-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 41.
PIC18F97J60 FAMILY TABLE 28-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.6V TO 3.6V) Sym Characteristic Min Typ† Max Units Conditions F10 FOSC Oscillator Frequency Range 8 8 — — 25 37.5 MHz HSPLL mode MHz ECPLL mode F11 FSYS On-Chip VCO System Frequency 20 — 62.5 MHz F12 trc PLL Start-up Time (Lock Time) — — 2 ms F13 CLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 3.3V, 25C, unless otherwise stated.
PIC18F97J60 FAMILY FIGURE 28-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 12 14 18 19 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Refer to Figure 28-3 for load conditions. Note: TABLE 28-9: Param No.
PIC18F97J60 FAMILY FIGURE 28-6: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 AD<15:0> Address Address Address Data from External 150 151 Address 163 160 162 161 155 166 167 ALE 168 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C, unless otherwise stated. TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.
PIC18F97J60 FAMILY FIGURE 28-7: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address 166 AD<15:0> Data Address Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C, unless otherwise stated. TABLE 28-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.
PIC18F97J60 FAMILY FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 28-3 for load conditions. TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No.
PIC18F97J60 FAMILY FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 28-3 for load conditions. TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F97J60 FAMILY FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCPx MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 28-3 for load conditions. TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCPx MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18F97J60 FAMILY FIGURE 28-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKP = 0) 78 79 79 78 SCKx (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 28-3 for load conditions. TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F97J60 FAMILY FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 80 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 28-3 for load conditions. TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F97J60 FAMILY FIGURE 28-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx SDI 77 bit 6 - - - - 1 LSb In 74 73 Refer to Figure 28-3 for load conditions. Note: TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F97J60 FAMILY FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDI SDIx MSb In 77 bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 28-3 for load conditions. TABLE 28-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F97J60 FAMILY FIGURE 28-15: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-3 for load conditions. TABLE 28-20: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F97J60 FAMILY TABLE 28-21: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol No. 100 THIGH 101 TLOW 102 TR 103 TF 90 91 106 Characteristic Clock High Time Clock Low Time 110 2: — s PIC18F97J60 family must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18F97J60 family must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 100 kHz mode 4.7 — s PIC18F97J60 family must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC18F97J60 FAMILY FIGURE 28-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-3 for load conditions. TABLE 28-22: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F97J60 FAMILY TABLE 28-23: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms — 1000 ns 20 + 0.
PIC18F97J60 FAMILY FIGURE 28-19: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 28-3 for load conditions. TABLE 28-24: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F97J60 FAMILY TABLE 28-26: A/D CONVERTER CHARACTERISTICS: PIC18F97J60 FAMILY (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units — — 10 bit Conditions VREF 2.0V A01 NR Resolution A03 EIL Integral Linearity Error — — <±1 LSb VREF 2.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF 2.0V A06 EOFF Offset Error — — <±3 LSb VREF 2.0V A07 EGN Gain Error — — <±3 LSb VREF 2.
PIC18F97J60 FAMILY TABLE 28-27: A/D CONVERSION REQUIREMENTS Param Symbol No. Characteristic Min Max Units 0.7 25.0(1) s TOSC based, VREF 2.0V A/D RC mode 130 TAD A/D Clock Period TBD 1 s 131 TCNV Conversion Time (not including acquisition time) (Note 2) 11 12 TAD s 132 TACQ Acquisition Time (Note 3) 1.4 — 135 TSWC Switching Time from Convert Sample — (Note 4) TBD TDIS Discharge Time 0.2 — Legend: Note 1: 2: 3: 4: 28.
PIC18F97J60 FAMILY NOTES: DS39762F-page 464 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information Example 64-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F67J60I/PT e3 1110017 Example 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F97J60 FAMILY 29.2 Package Details The following sections give the technical details of the packages.
PIC18F97J60 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY ) ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b NOTE 1 12 3 NOTE 2 c φ β L α A A2 A1 L1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 8 89 : @ / 1 + = = / / / = / 3 & 7 & 7 / ; / 3 & & 7 # # 4 4
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PIC18F97J60 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E1 E b N NOTE 1 α 1 23 A NOTE 2 φ c β A2 A1 L L1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 8 89 : / 1 + = = / / / = / 3 & 7 & 7 / ; / 3 & & 7 # # 4 4
PIC18F97J60 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY NOTES: DS39762F-page 474 2011 Microchip Technology Inc.
PIC18F97J60 FAMILY APPENDIX A: REVISION HISTORY Revision A (March 2006) Original data sheet for the PIC18F97J60 family of devices. Revision B (October 2006) First revision. Includes preliminary electrical specifications; revised and updated material on the Ethernet module; updated material on Reset integration; and updates to the device memory map. Revision C (June 2007) Corrected Table 10.
PIC18F97J60 FAMILY APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1.
PIC18F97J60 FAMILY INDEX A A/D ................................................................................... 339 Acquisition Requirements ........................................ 344 ADCAL Bit ................................................................ 347 ADCON0 Register .................................................... 339 ADCON1 Register .................................................... 339 ADCON2 Register .................................................... 339 ADRESH Register .........
PIC18F97J60 FAMILY BSF .................................................................................. 387 BTFSC ............................................................................. 388 BTFSS .............................................................................. 388 BTG .................................................................................. 389 BZ ..................................................................................... 390 C C Compilers MPLAB C18 ................
PIC18F97J60 FAMILY Memory Maps Ethernet Special Function Registers ................. 90 PIC18F97J60 Family ......................................... 87 Special Function Registers ................................ 89 Special Function Registers ........................................ 89 DAW ................................................................................. 394 DC Characteristics ........................................................... 439 Power-Down and Supply Current .......................
PIC18F97J60 FAMILY Transmitting and Receiving Data ............................. 247 Packet Field Definitions ........................... 247–248 Reading Received Packets .............................. 253 Receive Buffer Space ...................................... 254 Receive Packet Layout .................................... 252 Receive Status Vectors .................................... 253 Receiving Packets ........................................... 252 Transmit Packet Layout ..........................
PIC18F97J60 FAMILY Master Mode ............................................................ 298 Baud Rate Generator ....................................... 300 Operation ......................................................... 299 Reception ......................................................... 304 Repeated Start Condition Timing ..................... 303 Start Condition Timing ..................................... 302 Transmission ...................................................
PIC18F97J60 FAMILY Interrupt Sources .............................................................. 359 Interrupt-on-Change (RB7:RB4) .............................. 148 INTx Pin ................................................................... 144 PORTB, Interrupt-on-Change .................................. 144 TMR0 ....................................................................... 144 TMR0 Overflow ........................................................ 173 TMR1 Overflow ..........................
PIC18F97J60 FAMILY RD2/CCP4/P3D ......................................................... 21 RD3/AD3/PSP3 .......................................................... 36 RD4/AD4/PSP4/SDO2 ............................................... 36 RD5/AD5/PSP5/SDI2/SDA2 ...................................... 36 RD6/AD6/PSP6/SCK2/SCL2 ..................................... 36 RD7/AD7/PSP7/SS2 .................................................. 36 RE0/AD8/RD/P2D ......................................................
PIC18F97J60 FAMILY PORTJ Associated Registers ............................................... 167 LATJ Register .......................................................... 166 PORTJ Register ....................................................... 166 TRISJ Register ......................................................... 166 Power-Managed Modes ..................................................... 55 and SPI Operation ................................................... 277 Clock Sources ....................
PIC18F97J60 FAMILY ECON1 (Ethernet Control 1) .................................... 227 ECON2 (Ethernet Control 2) .................................... 228 EECON1 (EEPROM Control 1) ................................ 107 EFLOCON (Ethernet Flow Control) ......................... 258 EIE (Ethernet Interrupt Enable) ................................ 240 EIR (Ethernet Interrupt Request, Flag) .................... 241 ERXFCON (Ethernet Receive Filter Control) ........... 260 ESTAT (Ethernet Status) .................
PIC18F97J60 FAMILY Serial Clock .............................................................. 269 Serial Data In ........................................................... 269 Serial Data Out ........................................................ 269 Slave Mode .............................................................. 275 Slave Select ............................................................. 269 Slave Select Synchronization .................................. 275 SPI Clock ......................
PIC18F97J60 FAMILY I2C Bus Collision During a Stop Condition (Case 2) ........................................... 312 I2C Bus Collision During Start Condition (SCLx = 0) ....................................... 310 I2C Bus Collision During Start Condition (SDAx Only) ..................................... 309 I2C Bus Collision for Transmit and Acknowledge .... 308 I2C Bus Data ............................................................ 457 I2C Bus Start/Stop Bits .............................................
PIC18F97J60 FAMILY NOTES: DS39762F-page 488 2011 Microchip Technology Inc.
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PIC18F97J60 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device PIC18F66J60/66J65/67J60, PIC18F86J60/86J65/87J60, PIC18F96J60/96J65/97J60, PIC18F66J60/66J65/67J60T(1), PIC18F86J60/86J65/87J60T(1), PIC18F96J60/96J65/97J60T(1) Temperature Range I Package PT = = PF = Pattern Examples: a) b) PIC18F67J60-I/PT 301 = Industrial temp.
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