Datasheet

PIC18F87K22 FAMILY
DS39960B-page 542 Preliminary  2010 Microchip Technology Inc.
Special Event Trigger.
See Compare (ECCP Mode).
SPI Mode (MSSP)............................................................. 279
Associated Registers ................................................288
Bus Mode Compatibility ............................................ 287
Clock Speed, Interactions ......................................... 287
Effects of a Reset......................................................287
Enabling SPI I/O .......................................................283
Master Mode ............................................................. 284
Master/Slave Connection .......................................... 283
Operation .................................................................. 282
Operation in Power-Managed Modes ....................... 287
Serial Clock...............................................................279
Serial Data In ............................................................ 279
Serial Data Out ......................................................... 279
Slave Mode ............................................................... 285
Slave Select .............................................................. 279
Slave Select Synchronization ................................... 285
SPI Clock .................................................................. 284
SSPxBUF Register ...................................................284
SSPxSR Register...................................................... 284
Typical Connection ................................................... 283
SSPOV.............................................................................. 315
SSPOV Status Flag...........................................................315
SSPxSTAT Register
R/W
Bit.............................................................. 294, 297
SSx
.................................................................................... 279
Stack Full/Underflow Resets ............................................... 89
SUBFSR............................................................................475
SUBFWB...........................................................................464
SUBLW ............................................................................. 465
SUBULNK .........................................................................475
SUBWF .............................................................................465
SUBWFB...........................................................................466
SWAPF ............................................................................. 466
T
Table Pointer Operations (table)....................................... 112
Table Reads/Table Writes................................................... 89
TBLRD .............................................................................. 467
TBLWT.............................................................................. 468
Timer0............................................................................... 191
Associated Registers ................................................193
Operation .................................................................. 192
Overflow Interrupt ..................................................... 193
Prescaler...................................................................193
Switching Assignment....................................... 193
Prescaler Assignment (PSA Bit) ............................... 193
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 193
Reads and Writes in 16-Bit Mode ............................. 192
Source Edge Select (T0SE Bit)................................. 192
Source Select (T0CS Bit).......................................... 192
Timer1............................................................................... 195
16-Bit Read/Write Mode............................................ 199
Associated Registers ................................................205
Clock Source Selection.............................................197
Gate .......................................................................... 201
Interrupt.....................................................................200
Operation .................................................................. 197
Oscillator ................................................................... 195
SOSC Layout Considerations...........................200
Oscillator, as Secondary Clock ................................... 46
Resetting, Using the ECCP Special
Event Trigger .................................................... 201
SOSC Oscillator........................................................ 199
TMR1H Register ....................................................... 195
TMR1L Register........................................................195
Using SOSC as a Clock Source ............................... 200
Timer2............................................................................... 207
Associated Registers................................................ 208
Interrupt .................................................................... 208
Operation.................................................................. 207
Output....................................................................... 208
PR2 Register ............................................................ 253
TMR2 to PR2 Match Interrupt................................... 253
Timer3/5/7......................................................................... 209
16-Bit Read/Write Mode ........................................... 214
Associated Registers................................................ 220
Gates ........................................................................ 215
Operation.................................................................. 213
Oscillator................................................................... 209
Overflow Interrupt ............................................. 209, 219
Special Event Trigger (ECCP).................................. 219
TMRxH Register ....................................................... 209
TMRxL Register........................................................ 209
Using SOSCO Oscillator as Clock Source ............... 214
Timer4
MSSP Clock Shift ..................................................... 222
Timer4/6/8/10/12............................................................... 221
Associated Registers................................................ 223
Interrupt .................................................................... 222
Operation.................................................................. 221
Output....................................................................... 222
Postscaler.
See Postscaler, Timer4/6/8/10/12.
Prescaler.
See Prescaler, Timer4/6/8/10/12.
PRx Register............................................................. 221
TMRx Register.......................................................... 221
Timing Diagrams
A/D Conversion......................................................... 521
Asynchronous Reception.......................................... 339
Asynchronous Transmission..................................... 336
Asynchronous Transmission (Back-to-Back)............ 336
Automatic Baud Rate Calculation ............................. 334
Auto-Wake-up Bit (WUE) During Normal
Operation.......................................................... 341
Auto-Wake-up Bit (WUE) During Sleep.................... 341
Baud Rate Generator with Clock Arbitration............. 312
BRG Overflow Sequence.......................................... 334
BRG Reset Due to SDAx Arbitration During
Start Condition.................................................. 321
Brown-out Reset (BOR)............................................ 507
Bus Collision During Repeated Start
Condition (Case 1)............................................ 322
Bus Collision During Repeated Start
Condition (Case 2)............................................ 322
Bus Collision During Start Condition
(SCLx = 0) ........................................................ 321
Bus Collision During Start Condition
(SDAx Only)...................................................... 320
Bus Collision During Stop Condition (Case 1) .......... 323
Bus Collision During Stop Condition (Case 2) .......... 323
Bus Collision for Transmit and Acknowledge ........... 319
Capture/Compare/PWM ........................................... 510
CLKO and I/O ........................................................... 503
Clock Synchronization .............................................. 305
Clock/Instruction Cycle ............................................... 90
EUSART Synchronous Receive
(Master/Slave) .................................................. 519
EUSART Synchronous Transmission
(Master/Slave) .................................................. 519
Example SPI Master Mode (CKE = 0) ...................... 511
Example SPI Master Mode (CKE = 1) ...................... 512