Datasheet

PIC18F87K22 FAMILY
DS39960B-page 28 Preliminary  2010 Microchip Technology Inc.
PORTD is a bidirectional I/O port.
RD0/CTPLS
RD0
CTPLS
72
I/O
O
ST
ST
Digital I/O.
CTMU pulse generator output.
RD1/T5CKI/T7G
RD1
T5CKI
T7G
69
I/O
I
I
ST
ST
ST
Digital I/O.
Timer5 clock input.
Timer7 external clock gate input.
RD2/PSP2/AD2
RD2
PSP2
(4)
AD2
68
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External Memory Address Data 2.
RD3/PSP3/AD3
RD3
PSP3
(4)
AD3
67
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External Memory Address Data 3.
RD4/SDO2/PSP4/AD4
RD4
SDO2
PSP4
(4)
AD4
66
I/O
O
I/O
I/O
ST
—
TTL
TTL
Digital I/O.
SPI data out.
Parallel Slave Port data.
External Memory Address Data 4.
RD5/SDI2/SDA2/PSP5/
AD5
RD5
SDI2
SDA2
PSP5
(4)
AD5
65
I/O
I
I/O
I/O
I/O
ST
ST
I
2
C
TTL
TTL
Digital I/O.
SPI data in.
I
2
C™ data I/O.
Parallel Slave Port data.
External Memory Address Data 5.
TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C = I
2
C™/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K22 and PIC18F85K22 devices.
4: PSP is available only in Microcontroller mode.
5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).