Datasheet

PIC18F87K22 FAMILY
DS39960B-page 184 Preliminary  2010 Microchip Technology Inc.
TABLE 12-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
RH5/CCP8/
P3B/AN13/
C2IND
RH5 0 O DIG LATH<5> data output.
1 I ST PORTH<5> data input.
CCP8 0 O DIG CCP8 compare/PWM output. Takes priority over port data.
1 I ST CCP8 capture input.
P3B 0 O — ECCP3 PWM Output B.
May be configured for tri-state during Enhanced PWM.
AN13 1 I ANA A/D Input Channel 13.
Default input configuration on POR. Does not affect digital input.
C2IND x I ANA Comparator 2 Input D.
RH6/CCP7/
P1C/AN14/
C1INC
RH6 0 O DIG LATH<6> data output.
1 I ST PORTH<6> data input.
CCP7 0 O DIG CCP7 compare/PWM output. Takes priority over port data.
1 I ST CCP7 capture input.
P1C 0 O — ECCP1 PWM Output C.
May be configured for tri-state during Enhanced PWM.
AN14 1 I ANA A/D Input Channel 14.
Default input configuration on POR. Does not affect digital input.
C1INC x I ANA Comparator 1 Input C.
RH7/CCP6/
P1B/AN15
RH7 0 O DIG LATH<7> data output.
1 I ST PORTH<7> data input.
CCP6 0 O DIG CCP6 compare/PWM output. Takes priority over port data.
1 I ST CCP6 capture input.
P1B 0 O — ECCP1 PWM Output B.
May be configured for tri-state during Enhanced PWM.
AN15 1 I ANA A/D Input Channel 15.
Default input configuration on POR. Does not affect digital input.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0
LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0
TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0
ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12
ANSEL11 ANSEL10 ANSEL9 ANSEL8
ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16
ODCON2
CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD
TABLE 12-15: PORTH FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).