Datasheet

PIC18F66K80 FAMILY

DS39977C-page 76 Preliminary  2011 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPMD

(1)

CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 PSPMD: Peripheral Module Disable bit

(1)

1 = The PSP module is disabled. All PSP registers are held in Reset and are not writable.

0 = The PSP module is enabled

bit 6 CTMUMD: PMD CTMU Disable bit

1 = The CTMU module is disabled. All CTMU registers are held in Reset and are not writable.

0 = The CTMU module is enabled

bit 5 ADCMD: ADC Module Disable bit

1 = The ADC module is disabled. All ADC registers are held in Reset and are not writable.

0 = The ADC module is enabled

bit 4 TMR4MD: TMR4MD Disable bit

1 = The Timer4 module is disabled. All Timer4 registers are held in Reset and are not writable.

0 = The Timer4 module is enabled

bit 3 TMR3MD: TMR3MD Disable bit

1 = The Timer3 module is disabled. All Timer3 registers are held in Reset and are not writable.

0 = The Timer3 module is enabled

bit 2 TMR2MD: TMR2MD Disable bit

1 = The Timer2 module is disabled. All Timer2 registers are held in Reset and are not writable.

0 = The Timer2 module is enabled

bit 1 TMR1MD: TMR1MD Disable bit

1 = The Timer1 module is disabled. All Timer1 registers are held in Reset and are not writable.

0 = The Timer1 module is enabled

bit 0 TMR0MD: Timer0 Module Disable bit

1 = The Timer0 module is disabled. All Timer0 registers are held in Reset and are not writable.

0 = The Timer0 module is enabled

Note 1: Unimplemented on devices with 28-pin devices (PIC18F2XK80, PIC18LF2XK80).