Datasheet

PIC18F66K80 FAMILY
DS39977C-page 622 Preliminary  2011 Microchip Technology Inc.
Half-Bridge PWM Output .................................. 280, 287
High-Voltage Detect Operation
(VDIRMAG = 1).................................................393
HLVD Characteristics................................................ 575
I
2
C Acknowledge Sequence ..................................... 331
I
2
C Bus Data .............................................................583
I
2
C Bus Start/Stop Bits..............................................582
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 329
I
2
C Master Mode (7-Bit Reception) ........................... 330
I
2
C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) .............................................. 314
I
2
C Slave Mode (10-Bit Reception, SEN = 0) ........... 315
I
2
C Slave Mode (10-Bit Reception, SEN = 1) ........... 320
I
2
C Slave Mode (10-Bit Transmission)...................... 316
I
2
C Slave Mode (7-bit Reception, SEN = 0,
ADMSK = 01011) .............................................. 312
I
2
C Slave Mode (7-Bit Reception, SEN = 0) ............. 311
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............. 319
I
2
C Slave Mode (7-Bit Transmission)........................ 313
I
2
C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode)......... 321
I
2
C Stop Condition Receive or Transmit Mode ......... 331
Low-Voltage Detect Operation (VDIRMAG = 0)........ 392
MSSP Clock Synchronization ...................................318
MSSP I
2
C Bus Data.................................................. 584
MSSP I
2
C Bus Start/Stop Bits ..................................584
Parallel Slave Port (PSP) Read ................................200
Parallel Slave Port (PSP) Write ................................ 199
PWM Auto-Shutdown with Auto-Restart
Enabled............................................................. 286
PWM Auto-Shutdown with Firmware Restart............ 286
PWM Direction Change ............................................ 283
PWM Direction Change at Near 100%
Duty Cycle.........................................................284
PWM Output ............................................................. 268
Repeated Start Condition.......................................... 327
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ...... 573
Send Break Character Sequence ............................. 356
Slave Synchronization ..............................................299
Slow Rise Time (MCLR
Tied to VDD, VDD
Rise > T
PWRT).....................................................87
SPI Mode (Master Mode).......................................... 298
SPI Mode (Slave Mode, CKE = 0) ............................ 300
SPI Mode (Slave Mode, CKE = 1) ............................ 300
Steering Event at Beginning of Instruction
(STRSYNC = 1) ................................................ 290
Steering Event at End of Instruction
(STRSYNC = 0) ................................................ 290
Synchronous Reception (Master Mode, SREN) ....... 359
Synchronous Transmission....................................... 357
Synchronous Transmission (Through TXEN) ........... 358
Time-out Sequence on POR w/ PLL
Enabled (MCLR
Tied to VDD)..............................88
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1........................ 87
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2........................ 87
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise TPWRT) ............... 86
Timer0 and Timer1 External Clock ........................... 576
Timer1 Gate Count Enable Mode............................. 223
Timer1 Gate Single Pulse Mode............................... 225
Timer1 Gate Single Pulse/Toggle
Combined Mode ............................................... 226
Timer1 Gate Toggle Mode........................................ 224
Timer3 Gate Count Enable Mode............................. 234
Timer3 Gate Single Pulse Mode............................... 236
Timer3 Gate Single Pulse/Toggle
Combined Mode ............................................... 237
Timer3 Gate Toggle Mode........................................ 235
Transition for Entry to Idle Mode................................. 73
Transition for Entry to SEC_RUN Mode ..................... 69
Transition for Entry to Sleep Mode ............................. 72
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 480
Transition for Wake from Idle to Run Mode................ 73
Transition for Wake from Sleep (HSPLL) ................... 72
Transition from RC_RUN Mode to
PRI_RUN Mode.................................................. 71
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ................................... 69
Transition to RC_RUN Mode...................................... 71
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements.................... 577
CLKO and I/O Requirements............................ 572, 573
EUSART/AUSART Synchronous Receive
Requirements ................................................... 586
EUSART/AUSART Synchronous Transmission
Requirements ................................................... 586
Example SPI Mode Requirements
(Master Mode, CKE = 0)................................... 578
Example SPI Mode Requirements
(Master Mode, CKE = 1)................................... 579
Example SPI Mode Requirements
(Slave Mode, CKE = 0)..................................... 580
Example SPI Slave Mode Requirements
(CKE = 1).......................................................... 581
External Clock Requirements ................................... 570
HLVD Characteristics ............................................... 575
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2
C Bus Data Requirements (Slave Mode) ............... 583
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 582
Internal RC Accuracy (INTOSC)............................... 571
MSSP I
2
C Bus Data Requirements .......................... 585
MSSP I
2
C Bus Start/Stop Bits Requirements........... 584
PLL Clock ................................................................. 571
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 574
Timer0 and Timer1 External Clock
Requirements ................................................... 576
Top-of-Stack Access......................................................... 107
TSTFSZ ............................................................................ 527
Two-Speed Start-up.................................................. 461, 480
IESO (CONFIG1H, Internal/External
Oscillator Switchover Bit................................... 464
Two-Word Instructions
Example Cases......................................................... 111
TXSTAx Register
BRGH Bit .................................................................. 343