Datasheet

 2011 Microchip Technology Inc. Preliminary DS39977C-page 621
PIC18F66K80 FAMILY
SUBFSR ........................................................................... 533
SUBFWB........................................................................... 522
SUBLW ............................................................................. 523
SUBULNK ......................................................................... 533
SUBWF ............................................................................. 523
SUBWFB........................................................................... 524
SWAPF ............................................................................. 524
T
Table Pointer Operations (table)....................................... 138
Table Reads/Table Writes ................................................ 109
TBLRD .............................................................................. 525
TBLWT.............................................................................. 526
Time-out in Various Situations (table)................................. 86
Timer0............................................................................... 211
Associated Registers ................................................ 213
Operation .................................................................. 212
Overflow Interrupt ..................................................... 213
Prescaler................................................................... 213
Switching Assignment....................................... 213
Prescaler Assignment (PSA Bit) ............................... 213
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 213
Reads and Writes in 16-Bit Mode ............................. 212
Source Edge Select (T0SE Bit)................................. 212
Source Select (T0CS Bit).......................................... 212
Timer1............................................................................... 215
16-Bit Read/Write Mode............................................ 220
Associated Registers ................................................ 226
Clock Source Selection............................................. 218
Gate .......................................................................... 222
Interrupt..................................................................... 221
Operation .................................................................. 218
Oscillator................................................................... 215
Oscillator, as Secondary Clock ................................... 58
Resetting, Using the ECCP Special
Event Trigger .................................................... 222
SOSC Oscillator........................................................ 220
Layout Considerations ...................................... 221
Use as a Clock Source ..................................... 221
TMR1H Register ....................................................... 215
TMR1L Register........................................................ 215
Timer2............................................................................... 227
Associated Registers ................................................ 228
Interrupt..................................................................... 228
Operation .................................................................. 227
Output ....................................................................... 228
PR2 Register............................................................. 268
TMR2 to PR2 Match Interrupt................................... 268
Timer3............................................................................... 229
16-Bit Read/Write Mode............................................ 233
Associated Registers ................................................ 238
Gates ........................................................................ 234
Operation .................................................................. 232
Oscillator................................................................... 229
Overflow Interrupt ............................................. 229, 238
SOSC Oscillator
Use as the Timer3 Clock Source ...................... 233
Special Event Trigger (ECCP) .................................. 238
TMR3H Register ....................................................... 229
TMR3L Register........................................................ 229
Timer4 .............................................................................. 239
Associated Registers................................................ 240
Interrupt .................................................................... 240
Operation.................................................................. 239
Output....................................................................... 240
Postscaler.
See Postscaler, Timer4.
PR4 Register ............................................................ 239
Prescaler.
See Prescaler, Timer4.
TMR4 Register ......................................................... 239
Timing Diagrams
A/D Conversion ........................................................ 588
Asynchronous Reception.......................................... 353
Asynchronous Transmission .................................... 350
Asynchronous Transmission (Back-to-Back)............ 350
Automatic Baud Rate Calculation............................. 348
Auto-Wake-up Bit (WUE) During Normal
Operation.......................................................... 355
Auto-Wake-up Bit (WUE) During Sleep.................... 355
Baud Rate Generator with Clock Arbitration............. 325
BRG Overflow Sequence ......................................... 348
BRG Reset Due to SDA Arbitration During
Start Condition.................................................. 334
Brown-out Reset (BOR)............................................ 574
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 335
Bus Collision During a Repeated Start
Condition (Case 2)............................................ 335
Bus Collision During a Start Condition
(SCL = 0) .......................................................... 334
Bus Collision During a Stop Condition (Case 1)....... 336
Bus Collision During a Stop Condition (Case 2)....... 336
Bus Collision During Start Condition
(SDA Only) ....................................................... 333
Bus Collision for Transmit and Acknowledge ........... 332
Capture/Compare/PWM (ECCP1, ECCP2).............. 577
CLKO and I/O ........................................................... 572
Clock/Instruction Cycle............................................. 110
DSM Carrier High Synchronization (MDCHSYNC = 1,
MDCLSYNC = 0) .............................................. 204
DSM Carrier Low Synchronization
(MDCHSYNC = 0, MDCLSYNC = 1) ................ 205
DSM Full Synchronization
(MDCHSYNC = 1, MDCLSYNC = 1) ................ 205
DSM No Synchronization
(MDCHSYNC = 0, MDCLSYNC = 0) ................ 204
DSM On-Off Keying (OOK) Synchronization............ 204
Enhanced PWM Output (Active-High) ...................... 278
Enhanced PWM Output (Active-Low)....................... 279
EUSART Synchronous Transmission
(Master/Slave) .................................................. 586
EUSART/AUSART Synchronous Receive (Master/
Slave) ............................................................... 586
Example SPI Master Mode (CKE = 0)...................... 578
Example SPI Master Mode (CKE = 1)...................... 579
Example SPI Slave Mode (CKE = 0)........................ 580
Example SPI Slave Mode (CKE = 1)........................ 581
External Clock .......................................................... 570
Fail-Safe Clock Monitor (FSCM)............................... 482
First Start Bit Timing ................................................. 326
Full-Bridge PWM Output........................................... 282