Datasheet

PIC18F66K80 FAMILY
DS39977C-page 620 Preliminary  2011 Microchip Technology Inc.
RXBnEIDL (Receive Buffer n Extended
Identifier, Low Byte) .......................................... 414
RXBnSIDH (Receive Buffer n Standard
Identifier, High Byte) ......................................... 413
RXBnSIDL (Receive Buffer n Standard
Identifier, Low Byte) .......................................... 414
RXERRCNT (Receive Error Count) .......................... 416
RXFBCONn (Receive Filter Buffer Control n) ........... 429
RXFCONn (Receive Filter Control n) ........................ 428
RXFnEIDH (Receive Acceptance Filter n
Extended Identifier, High Byte) ......................... 426
RXFnEIDL (Receive Acceptance Filter n
Extended Identifier, Low Byte) .......................... 426
RXFnSIDH (Receive Acceptance Filter n
Standard Identifier Filter, High Byte)................. 425
RXFnSIDL (Receive Acceptance Filter n
Standard Identifier Filter, Low Byte).................. 425
RXMnEIDH (Receive Acceptance Mask n
Extended Identifier Mask, High Byte)................ 427
RXMnEIDL (Receive Acceptance Mask n
Extended Identifier Mask, Low Byte) ................ 427
RXMnSIDH (Receive Acceptance Mask n
Standard Identifier Mask, High Byte) ................ 426
RXMnSIDL (Receive Acceptance Mask n
Standard Identifier Mask, Low Byte) ................. 427
SDFLC (Standard Data Bytes Filter
Length Count) ................................................... 428
SLRCON (Slew Rate Control)...................................180
SSPCON1 (MSSP Control 1, I
2
C Mode) .................. 304
SSPCON1 (MSSP Control 1, SPI Mode).................. 295
SSPCON2 (MSSP Control 2, I
2
C Master Mode) ...... 305
SSPCON2 (MSSP Control 2, I
2
C Slave Mode) ........ 306
SSPMSK (I
2
C Slave Address Mask).........................306
SSPSTAT (MSSP Status, I
2
C Mode)........................ 303
SSPSTAT (MSSP Status, SPI Mode) ....................... 294
STATUS....................................................................127
STKPTR (Stack Pointer) ...........................................108
T0CON (Timer0 Control)........................................... 211
T1CON (Timer1 Control)........................................... 215
T1GCON (Timer1 Gate Control) ............................... 217
T2CON (Timer2 Control)........................................... 227
T3CON (Timer3 Control)........................................... 229
T3GCON (Timer3 Gate Control) ............................... 230
T4CON (Timer4 Control)........................................... 239
TXBIE (Transmit Buffers Interrupt Enable) ............... 441
TXBnCON (Transmit Buffer n Control) ..................... 404
TXBnDLC (Transmit Buffer n
Data Length Code)............................................ 407
TXBnDm (Transmit Buffer n Data Field Byte m).......406
TXBnEIDH (Transmit Buffer n Extended
Identifier, High Byte) ......................................... 405
TXBnEIDL (Transmit Buffer n Extended
Identifier, Low Byte) .......................................... 406
TXBnSIDH (Transmit Buffer n Standard
Identifier, High Byte) ......................................... 405
TXBnSIDL (Transmit Buffer n Standard
Identifier, Low Byte) .......................................... 405
TXERRCNT (Transmit Error Count).......................... 407
TXSTAx (Transmit Status and Control) .................... 340
WDTCON (Watchdog Timer Control)........................ 477
WPUB (Weak Pull-up PORTB Enable)..................... 178
RESET.............................................................................. 517
Resets......................................................................... 81, 461
Brown-out Reset (BOR)............................................ 461
Oscillator Start-up Timer (OST)................................ 461
Power-on Reset (POR)............................................. 461
Power-up Timer (PWRT) .......................................... 461
RETFIE ............................................................................. 518
RETLW ............................................................................. 518
RETURN........................................................................... 519
Return Address Stack....................................................... 107
Return Stack Pointer (STKPTR) ....................................... 108
Revision History................................................................ 609
RLCF ................................................................................ 519
RLNCF.............................................................................. 520
RRCF................................................................................ 520
RRNCF ............................................................................. 521
S
SCK .................................................................................. 293
SDI.................................................................................... 293
SDO.................................................................................. 293
SEC_IDLE Mode ................................................................ 73
SEC_RUN Mode................................................................. 68
Selective Peripheral Module Control .................................. 74
Serial Clock, SCK ............................................................. 293
Serial Data In (SDI)........................................................... 293
Serial Data Out (SDO) ...................................................... 293
Serial Peripheral Interface.
See SPI Mode.
SETF................................................................................. 521
Shoot-Through Current..................................................... 287
Slave Select (SS
).............................................................. 293
SLEEP .............................................................................. 522
Sleep Mode......................................................................... 72
Software Simulator (MPLAB SIM) .................................... 539
Special Event Trigger.
See Compare (CCP Module).
Special Event Trigger.
See Compare (ECCP Mode).
SPI Mode (MSSP) ............................................................ 293
Associated Registers................................................ 301
Bus Mode Compatibility ............................................ 301
Effects of a Reset ..................................................... 301
Enabling SPI I/O ....................................................... 297
Master Mode............................................................. 298
Master/Slave Connection.......................................... 297
Operation.................................................................. 296
Operation in Power-Managed Modes....................... 301
Serial Clock............................................................... 293
Serial Data In............................................................ 293
Serial Data Out ......................................................... 293
Slave Mode............................................................... 299
Slave Select.............................................................. 293
Slave Select Synchronization ................................... 299
SPI Clock.................................................................. 298
SSPBUF Register..................................................... 298
SSPSR Register ....................................................... 298
Typical Connection ................................................... 297
.......................................................................................... 293
SSPOV ............................................................................. 328
SSPOV Status Flag .......................................................... 328
SSPSTAT Register
R/W
Bit ............................................................. 307, 310
Stack Full/Underflow Resets............................................. 109