Datasheet

 2011 Microchip Technology Inc. Preliminary DS39977C-page 615
PIC18F66K80 FAMILY
F
Fail-Safe Clock Monitor............................................. 461, 481
Exiting Operation ...................................................... 481
Interrupts in Power-Managed Modes........................ 482
POR or Wake from Sleep ......................................... 482
WDT During Oscillator Failure .................................. 481
Fast Register Stack........................................................... 109
Firmware Instructions........................................................ 487
Flash Program Memory .................................................... 135
Associated Registers ................................................ 143
Control Registers ...................................................... 136
EECON1 and EECON2 .................................... 136
TABLAT (Table Latch) Register........................ 138
TBLPTR (Table Pointer) Register..................... 138
Erase Sequence ....................................................... 140
Erasing...................................................................... 140
Operation During Code-Protect ................................ 143
Reading..................................................................... 139
Table Pointer
Boundaries Based on Operation....................... 138
Table Pointer Boundaries ......................................... 138
Table Reads and Table Writes ................................. 135
Write Sequence ........................................................ 141
Writing....................................................................... 141
Protection Against Spurious Writes .................. 143
Unexpected Termination................................... 143
Write Verify ....................................................... 143
FSCM.
See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 508
H
Hardware Multiplier ........................................................... 151
8 x 8 Multiplication Algorithms .................................. 151
Operation .................................................................. 151
Performance Comparison (table).............................. 151
High/Low-Voltage Detect .................................................. 389
Applications............................................................... 393
Associated Registers ................................................ 394
Current Consumption................................................ 391
Effects of a Reset...................................................... 394
Operation .................................................................. 390
During Sleep ..................................................... 394
Setup......................................................................... 391
Start-up Time ............................................................ 391
Typical Application.................................................... 393
HLVD.
See High/Low-Voltage Detect. .............................. 389
I
I/O Descriptions
PIC18F2XK80............................................................. 20
PIC18F4XK80............................................................. 26
PIC18F6XK80............................................................. 35
I/O Ports............................................................................ 177
Analog, Digital Ports ................................................. 180
Open-Drain Outputs.................................................. 179
Output Pin Drive........................................................ 177
Pin Capabilities ......................................................... 177
Port Slew Rate.......................................................... 180
Pull-up Configuration ................................................ 177
I
2
C Mode (MSSP)
Acknowledge Sequence Timing................................ 331
Associated Registers ................................................ 337
Baud Rate Generator................................................ 324
Bus Collision
During a Repeated Start Condition................... 335
During a Stop Condition ................................... 336
Clock Arbitration ....................................................... 325
Clock Stretching ....................................................... 317
10-Bit Slave Receive Mode (SEN = 1) ............. 317
10-Bit Slave Transmit Mode ............................. 317
7-Bit Slave Receive Mode (SEN = 1) ............... 317
7-Bit Slave Transmit Mode ............................... 317
Clock Synchronization and the CKP bit.................... 318
Effects of a Reset ..................................................... 332
General Call Address Support.................................. 321
I
2
C Clock Rate w/BRG ............................................. 324
Master Mode............................................................. 322
Operation.......................................................... 323
Reception ......................................................... 328
Repeated Start Condition Timing ..................... 327
Start Condition Timing...................................... 326
Transmission .................................................... 328
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 332
Multi-Master Mode.................................................... 332
Operation.................................................................. 307
Read/Write
Bit Information (R/W Bit)................ 307, 310
Registers .................................................................. 302
Serial Clock (RC3REFO//SCL/SCK) ........................ 310
Slave Mode............................................................... 307
Address Masking Modes
5-Bit .......................................................... 308
7-Bit .......................................................... 309
Addressing ....................................................... 307
Reception ......................................................... 310
Transmission .................................................... 310
Sleep Operation........................................................ 332
Stop Condition Timing .............................................. 331
ID Locations.............................................................. 461, 486
Idle Modes .......................................................................... 72
INCF ................................................................................. 508
INCFSZ............................................................................. 509
In-Circuit Debugger........................................................... 486
In-Circuit Serial Programming (ICSP)....................... 461, 486
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 534
Indexed Literal Offset Mode.............................................. 534
Indirect Addressing........................................................... 129
INFSNZ............................................................................. 509
Initialization Conditions for all Registers............................. 90
Instruction Cycle ............................................................... 110
Clocking Scheme...................................................... 110
Flow/Pipelining ......................................................... 110
Instruction Set................................................................... 487
ADDLW..................................................................... 493
ADDWF .................................................................... 493
ADDWF (Indexed Literal Offset Mode)..................... 535
ADDWFC.................................................................. 494
ANDLW..................................................................... 494
ANDWF .................................................................... 495
BC............................................................................. 495
BCF .......................................................................... 496
BN............................................................................. 496
BNC.......................................................................... 497
BNN.......................................................................... 497
BNOV ....................................................................... 498
BNZ .......................................................................... 498
BOV.......................................................................... 501