Datasheet
PIC18F66K80 FAMILY
DS39977C-page 614 Preliminary 2011 Microchip Technology Inc.
Error Detection..........................................................456
Acknowledge..................................................... 456
Bit......................................................................456
CRC ..................................................................456
Error Modes and Counters................................ 456
Error States.......................................................456
Form..................................................................456
Stuff Bit .............................................................456
Error Modes State (diagram) .................................... 457
Error Recognition Mode ............................................ 443
Filter-Mask Truth (table)............................................ 448
Functional Modes...................................................... 443
Mode 0 (Legacy Mode) ..................................... 443
Mode 1 (Enhanced Legacy Mode).................... 443
Mode 2 (Enhanced FIFO Mode) ....................... 444
Information Processing Time (IPT) ...........................453
Lengthening a Bit Period........................................... 454
Listen Only Mode ...................................................... 443
Loopback Mode ........................................................ 443
Message Acceptance Filters and Masks .......... 425, 448
Message Acceptance Mask and Filter
Operation .......................................................... 449
Message Reception .................................................. 447
Enhanced FIFO Mode....................................... 448
Priority............................................................... 447
Time-Stamping.................................................. 448
Normal Mode ............................................................ 442
Oscillator Tolerance .................................................. 455
Overview ...................................................................395
Phase Buffer Segments ............................................453
Programmable TX/RX and Auto-RTR Buffers .......... 417
Programming Time Segments .................................. 455
Propagation Segment ............................................... 453
Sample Point............................................................. 453
Shortening a Bit Period .............................................455
Synchronization ........................................................ 454
Hard ..................................................................454
Resynchronization ............................................ 454
Rules................................................................. 454
Synchronization Segment .........................................453
Time Quanta ............................................................. 453
Values for ICODE (table) .......................................... 458
Effect on Standard PIC18 Instructions .............................. 534
Effects of Power-Managed Modes on Various
Clock Sources............................................................. 65
Electrical Characteristics................................................... 541
Enhanced Capture/Compare/PWM (ECCP) ..................... 271
Capture Mode.
See Capture.
Compare Mode.
See Compare.
ECCP Mode and Timer Resources........................... 274
Enhanced PWM Mode .............................................. 277
Auto-Restart......................................................286
Auto-Shutdown .................................................284
Direction Change in Full-Bridge
Output Mode ............................................. 283
Full-Bridge Application ...................................... 281
Full-Bridge Mode............................................... 281
Half-Bridge Application ..................................... 280
Half-Bridge Application Examples..................... 287
Half-Bridge Mode .............................................. 280
Output Relationships (Active-High and
Active-Low) ...............................................278
Output Relationships Diagram .......................... 279
Programmable Dead-Band Delay ..................... 287
Shoot-Through Current..................................... 287
Start-up Considerations.................................... 284
Outputs and Configuration........................................ 274
Enhanced Capture/Compare/PWM (ECCP) and
Timer1/2/3/4 Associated Registers........................... 292
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART).
See EUSART.
Equations
16 x 16 Signed Multiplication Algorithm.................... 152
16 x 16 Unsigned Multiplication Algorithm................ 152
A/D Acquisition Time ................................................ 372
A/D Minimum Charging Time.................................... 372
Calculating the Minimum Required
Acquisition Time ............................................... 372
Errata .................................................................................. 11
Error Recognition Mode.................................................... 442
EUSART
Asynchronous Mode ................................................. 349
12-Bit Break Transmit and Receive.................. 356
Associated Registers, Receive......................... 353
Associated Registers, Transmit ........................ 351
Auto-Wake-up on Sync Break .......................... 354
Receiver ........................................................... 352
Setting up 9-Bit Mode with
Address Detect......................................... 352
Transmitter ....................................................... 349
Baud Rate Generator
Operation in Power-Managed Mode................. 343
Baud Rate Generator (BRG) .................................... 343
Associated Registers........................................ 344
Auto-Baud Rate Detect..................................... 347
Baud Rate Error, Calculating............................ 344
Baud Rates, Asynchronous Modes .................. 345
High Baud Rate Select (BRGH Bit) .................. 343
Sampling........................................................... 343
Synchronous Master Mode....................................... 357
Associated Registers, Receive......................... 360
Associated Registers, Transmit ........................ 358
Reception ......................................................... 359
Transmission .................................................... 357
Synchronous Slave Mode......................................... 361
Associated Registers, Receive......................... 362
Associated Registers, Transmit ........................ 361
Reception ......................................................... 362
Transmission .................................................... 361
Extended Instruction Set
ADDFSR................................................................... 530
ADDULNK................................................................. 530
CALLW ..................................................................... 531
MOVSF..................................................................... 531
MOVSS..................................................................... 532
PUSHL...................................................................... 532
SUBFSR ................................................................... 533
SUBULNK................................................................. 533
External Oscillator Modes
Clock Input (EC Modes).............................................. 61
HS............................................................................... 60