Datasheet

 2011 Microchip Technology Inc. Preliminary DS39977C-page 51
PIC18F66K80 FAMILY
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins and other signals
in close proximity to the oscillator are benign (i.e., free
of high frequencies, short rise and fall times, and other
similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro
®
Devices”
• AN849, “Basic PICmicro
®
Oscillator Design”
• AN943, “Practical PICmicro
®
Oscillator Analysis
and Design”
• AN949, “Making Your Oscillator Work”
2.7 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
FIGURE 2-4: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
GND
`
`
`
OSC1
OSC2
T1OSO
T1OS I
Copper Pour
Primary Oscillator
Crystal
Timer1 Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
T1 Oscillator: C1
T1 Oscillator: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)