Datasheet
2011 Microchip Technology Inc. Preliminary DS39977C-page 49
PIC18F66K80 FAMILY
2.4 Voltage Regulator Pins
(V
CAP/VDDCORE)
On the PIC18F66K80 family devices, the regulator is
enabled and a low-ESR (< 5Ω) capacitor is required on
the VCAP/VDDCORE pin to stabilize the voltage regulator
output voltage. The V
CAP/VDDCORE pin must not be
connected to V
DD and must use a capacitor of 10 μF
connected to ground. The type can be ceramic or
tantalum. Suitable examples of capacitors are shown in
Table 2-1. Capacitors with equivalent specifications
can be used. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 31.0 “Electrical
Characteristics” for additional information.
When the regulator is disabled, a 0.1F capacitor
should be connected from the V
CAP/VDDCORE pin to
ground. This capacitor’s characteristics must be similar
to those of the “decoupling” capacitors explained in
Section 2.2.1. For details on the V
DD requirement,
when the regulator is disabled, see Parameter D001 in
Section 31.0 “Electrical Characteristics”.
Some PIC18FXXKXX families or some devices within
a family do not provide the option of enabling or
disabling the on-chip voltage regulator:
•The PIC18LFXXKXX devices permanently
disable the voltage regulator.
These devices require a 0.1F capacitor on the
V
CAP/VDDCORE pin. The VDD level of these
devices must comply with the “voltage regulator
disabled” specification for Parameter D001, in
Section 31.0 “Electrical Characteristics”.
• PIC18FXXKXX devices permanently enable the
voltage regulator.
These devices require a 10 F capacitor on the
V
CAP/VDDCORE pin.
For details on all members of the PIC18F66K80 family,
see Section 28.3 “On-Chip Voltage Regulator”.
FIGURE 2-3: FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED V
CAP
2.5 ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(V
IH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 “Development Support”.
10
1
0.1
0.01
0.001
0.01 0.1 1 10 100 1000 10,000
Frequency (MHz)
ESR ()
Note: Typical data measurement at 25°C, 0V DC bias.