Datasheet

PIC18F66K80 FAMILY
DS39977C-page 438 Preliminary  2011 Microchip Technology Inc.
27.2.6 CAN INTERRUPT REGISTERS
The registers in this section are the same as described
in
Section 10.0 “Interrupts”. They are duplicated here
for convenience.
REGISTER 27-56: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5
Mode 0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
IRXIF WAKIF ERRIF TXB2IF TXB1IF
(1)
TXB0IF
(1)
RXB1IF RXB0IF
Mode 1,2
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
IRXIF WAKIF ERRIF TXBnIF TXB1IF
(1)
TXB0IF
(1)
RXBnIF FIFOWMIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7
IRXIF: CAN Bus Error Message Received Interrupt Flag bit
1 = An invalid message has occurred on the CAN bus
0 = No invalid message on the CAN bus
bit 6
WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = Activity on the CAN bus has occurred
0 = No activity on the CAN bus
bit 5
ERRIF: CAN Module Error Interrupt Flag bit
1 = An error has occurred in the CAN module (multiple sources; refer to Section 27.15.6 “Error Interrupt”)
0 = No CAN module errors
bit 4 When CAN is in Mode 0:
TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit
1 = Transmit Buffer 2 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 2 has not completed transmission of a message
When CAN is in Mode 1 or 2:
TXBnIF: Any Transmit Buffer Interrupt Flag bit
1 = One or more transmit buffers have completed transmission of a message and may be reloaded
0 = No transmit buffer is ready for reload
bit 3
TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit
(1)
1 = Transmit Buffer 1 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 1 has not completed transmission of a message
bit 2
TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit
(1)
1 = Transmit Buffer 0 has completed transmission of a message and may be reloaded
0 = Transmit Buffer 0 has not completed transmission of a message
bit 1 When CAN is in Mode 0:
RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit
1 = Receive Buffer 1 has received a new message
0 = Receive Buffer 1 has not received a new message
When CAN is in Mode 1 or 2:
RXBnIF: Any Receive Buffer Interrupt Flag bit
1 = One or more receive buffers has received a new message
0 = No receive buffer has received a new message
bit 0 When CAN is in Mode 0:
RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit
1 = Receive Buffer 0 has received a new message
0 = Receive Buffer 0 has not received a new message
When CAN is in Mode 1:
Unimplemented: Read as ‘0’
When CAN is in Mode 2:
FIFOWMIF: FIFO Watermark Interrupt Flag bit
1 = FIFO high watermark is reached
0 = FIFO high watermark is not reached
Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’.