Datasheet

 2011 Microchip Technology Inc. Preliminary DS39977C-page 367
PIC18F66K80 FAMILY
23.2.2 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is where the 12-bit
A/D result and extended sign bits (ADSGN) are loaded
at the completion of a conversion. This register pair is
16 bits wide. The A/D module gives the flexibility of left
or right justifying the 12-bit result in the 16-bit result
register. The A/D Format Select bit (ADFM) controls
this justification.
Figure 23-3 shows the operation of the A/D result justi-
fication and location of the extended sign bits
(ADSGN). The extended sign bits allow for easier
16-bit math to be performed on the result.
When the A/D Converter is disabled, these 8-bit
registers can be used as two, general purpose registers.
FIGURE 23-3: A/D RESULT JUSTIFICATION
REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES11 ADRES10 ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4
bit 7
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ADRES<11:4>: A/D Result High Byte bits
Result bits ADSGN bits
ADRESH ADRESL ADRESH ADRESL
Right Justified
ADFM = 1
Left Justified
ADFM = 0
12-Bit Result
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